Lines Matching refs:uint32_t
13 uint32_t gpio0a_iomux_sel_0; /* address offset: 0x0000 */
14 uint32_t gpio0a_iomux_sel_1; /* address offset: 0x0004 */
15 uint32_t reserved0008[62]; /* address offset: 0x0008 */
16 uint32_t gpio0a_ds_0; /* address offset: 0x0100 */
17 uint32_t gpio0a_ds_1; /* address offset: 0x0104 */
18 uint32_t gpio0a_ds_2; /* address offset: 0x0108 */
19 uint32_t gpio0a_ds_3; /* address offset: 0x010c */
20 uint32_t reserved0110[60]; /* address offset: 0x0110 */
21 uint32_t gpio0a_pull; /* address offset: 0x0200 */
22 uint32_t reserved0204[63]; /* address offset: 0x0204 */
23 uint32_t gpio0a_ie; /* address offset: 0x0300 */
24 uint32_t reserved0304[63]; /* address offset: 0x0304 */
25 uint32_t gpio0a_smt; /* address offset: 0x0400 */
26 uint32_t reserved0404[63]; /* address offset: 0x0404 */
27 uint32_t gpio0a_sus; /* address offset: 0x0500 */
28 uint32_t reserved0504[63]; /* address offset: 0x0504 */
29 uint32_t gpio0a_sl; /* address offset: 0x0600 */
30 uint32_t reserved0604[63]; /* address offset: 0x0604 */
31 uint32_t gpio0a_od; /* address offset: 0x0700 */
32 uint32_t reserved0704[63]; /* address offset: 0x0704 */
33 uint32_t io_vsel; /* address offset: 0x0800 */
34 uint32_t grf_jtag_con0; /* address offset: 0x0804 */
35 uint32_t grf_jtag_con1; /* address offset: 0x0808 */
36 uint32_t reserved080c[61]; /* address offset: 0x080c */
37 uint32_t xin_con; /* address offset: 0x0900 */
44 uint32_t reserved0000[2]; /* address offset: 0x0000 */
45 uint32_t gpio0b_iomux_sel_0; /* address offset: 0x0008 */
46 uint32_t gpio0b_iomux_sel_1; /* address offset: 0x000c */
47 uint32_t reserved0010[64]; /* address offset: 0x0010 */
48 uint32_t gpio0b_ds_0; /* address offset: 0x0110 */
49 uint32_t gpio0b_ds_1; /* address offset: 0x0114 */
50 uint32_t gpio0b_ds_2; /* address offset: 0x0118 */
51 uint32_t reserved011c[58]; /* address offset: 0x011c */
52 uint32_t gpio0b_pull; /* address offset: 0x0204 */
53 uint32_t reserved0208[63]; /* address offset: 0x0208 */
54 uint32_t gpio0b_ie; /* address offset: 0x0304 */
55 uint32_t reserved0308[63]; /* address offset: 0x0308 */
56 uint32_t gpio0b_smt; /* address offset: 0x0404 */
57 uint32_t reserved0408[63]; /* address offset: 0x0408 */
58 uint32_t gpio0b_sus; /* address offset: 0x0504 */
59 uint32_t reserved0508[63]; /* address offset: 0x0508 */
60 uint32_t gpio0b_sl; /* address offset: 0x0604 */
61 uint32_t reserved0608[63]; /* address offset: 0x0608 */
62 uint32_t gpio0b_od; /* address offset: 0x0704 */
63 uint32_t reserved0708[62]; /* address offset: 0x0708 */
64 uint32_t io_vsel; /* address offset: 0x0800 */
65 uint32_t grf_jtag_con0; /* address offset: 0x0804 */
66 uint32_t grf_jtag_con1; /* address offset: 0x0808 */
73 uint32_t reserved0000[8]; /* address offset: 0x0000 */
74 uint32_t gpio1a_iomux_sel_0; /* address offset: 0x0020 */
75 uint32_t gpio1a_iomux_sel_1; /* address offset: 0x0024 */
76 uint32_t reserved0028[70]; /* address offset: 0x0028 */
77 uint32_t gpio1a_ds_0; /* address offset: 0x0140 */
78 uint32_t gpio1a_ds_1; /* address offset: 0x0144 */
79 uint32_t gpio1a_ds_2; /* address offset: 0x0148 */
80 uint32_t reserved014c[49]; /* address offset: 0x014c */
81 uint32_t gpio1a_pull; /* address offset: 0x0210 */
82 uint32_t reserved0214[63]; /* address offset: 0x0214 */
83 uint32_t gpio1a_ie; /* address offset: 0x0310 */
84 uint32_t reserved0314[63]; /* address offset: 0x0314 */
85 uint32_t gpio1a_smt; /* address offset: 0x0410 */
86 uint32_t reserved0414[63]; /* address offset: 0x0414 */
87 uint32_t gpio1a_sus; /* address offset: 0x0510 */
88 uint32_t reserved0514[63]; /* address offset: 0x0514 */
89 uint32_t gpio1a_sl; /* address offset: 0x0610 */
90 uint32_t reserved0614[63]; /* address offset: 0x0614 */
91 uint32_t gpio1a_od; /* address offset: 0x0710 */
92 uint32_t reserved0714[59]; /* address offset: 0x0714 */
93 uint32_t io_vsel_vccio3; /* address offset: 0x0800 */
100 uint32_t reserved0000[9]; /* address offset: 0x0000 */
101 uint32_t gpio1a_iomux_sel_1; /* address offset: 0x0024 */
102 uint32_t gpio1b_iomux_sel_0; /* address offset: 0x0028 */
103 uint32_t gpio1b_iomux_sel_1; /* address offset: 0x002c */
104 uint32_t reserved0030[71]; /* address offset: 0x0030 */
105 uint32_t gpio1a_ds_3; /* address offset: 0x014c */
106 uint32_t gpio1b_ds_0; /* address offset: 0x0150 */
107 uint32_t gpio1b_ds_1; /* address offset: 0x0154 */
108 uint32_t gpio1b_ds_2; /* address offset: 0x0158 */
109 uint32_t reserved015c[45]; /* address offset: 0x015c */
110 uint32_t gpio1a_pull; /* address offset: 0x0210 */
111 uint32_t gpio1b_pull; /* address offset: 0x0214 */
112 uint32_t reserved0218[62]; /* address offset: 0x0218 */
113 uint32_t gpio1a_ie; /* address offset: 0x0310 */
114 uint32_t gpio1b_ie; /* address offset: 0x0314 */
115 uint32_t reserved0318[62]; /* address offset: 0x0318 */
116 uint32_t gpio1a_smt; /* address offset: 0x0410 */
117 uint32_t gpio1b_smt; /* address offset: 0x0414 */
118 uint32_t reserved0418[62]; /* address offset: 0x0418 */
119 uint32_t gpio1a_sus; /* address offset: 0x0510 */
120 uint32_t gpio1b_sus; /* address offset: 0x0514 */
121 uint32_t reserved0518[62]; /* address offset: 0x0518 */
122 uint32_t gpio1a_sl; /* address offset: 0x0610 */
123 uint32_t gpio1b_sl; /* address offset: 0x0614 */
124 uint32_t reserved0618[62]; /* address offset: 0x0618 */
125 uint32_t gpio1a_od; /* address offset: 0x0710 */
126 uint32_t gpio1b_od; /* address offset: 0x0714 */
127 uint32_t reserved0718[58]; /* address offset: 0x0718 */
128 uint32_t io_vsel_vccio4; /* address offset: 0x0800 */
135 uint32_t reserved0000[16]; /* address offset: 0x0000 */
136 uint32_t gpio2a_iomux_sel_0; /* address offset: 0x0040 */
137 uint32_t gpio2a_iomux_sel_1; /* address offset: 0x0044 */
138 uint32_t gpio2b_iomux_sel_0; /* address offset: 0x0048 */
139 uint32_t reserved004c[77]; /* address offset: 0x004c */
140 uint32_t gpio2a_ds_0; /* address offset: 0x0180 */
141 uint32_t gpio2a_ds_1; /* address offset: 0x0184 */
142 uint32_t gpio2a_ds_2; /* address offset: 0x0188 */
143 uint32_t gpio2a_ds_3; /* address offset: 0x018c */
144 uint32_t gpio2b_ds_0; /* address offset: 0x0190 */
145 uint32_t gpio2b_ds_1; /* address offset: 0x0194 */
146 uint32_t reserved0198[34]; /* address offset: 0x0198 */
147 uint32_t gpio2a_pull; /* address offset: 0x0220 */
148 uint32_t gpio2b_pull; /* address offset: 0x0224 */
149 uint32_t reserved0228[62]; /* address offset: 0x0228 */
150 uint32_t gpio2a_ie; /* address offset: 0x0320 */
151 uint32_t gpio2b_ie; /* address offset: 0x0324 */
152 uint32_t reserved0328[62]; /* address offset: 0x0328 */
153 uint32_t gpio2a_smt; /* address offset: 0x0420 */
154 uint32_t gpio2b_smt; /* address offset: 0x0424 */
155 uint32_t reserved0428[62]; /* address offset: 0x0428 */
156 uint32_t gpio2a_sus; /* address offset: 0x0520 */
157 uint32_t gpio2b_sus; /* address offset: 0x0524 */
158 uint32_t reserved0528[62]; /* address offset: 0x0528 */
159 uint32_t gpio2a_sl; /* address offset: 0x0620 */
160 uint32_t gpio2b_sl; /* address offset: 0x0624 */
161 uint32_t reserved0628[62]; /* address offset: 0x0628 */
162 uint32_t gpio2a_od; /* address offset: 0x0720 */
163 uint32_t gpio2b_od; /* address offset: 0x0724 */
164 uint32_t reserved0728[54]; /* address offset: 0x0728 */
165 uint32_t io_vsel_vccio6; /* address offset: 0x0800 */
166 uint32_t misc_con; /* address offset: 0x0804 */
167 uint32_t reserved0808; /* address offset: 0x0808 */
168 uint32_t saradc_con0; /* address offset: 0x080c */
169 uint32_t saradc_con1; /* address offset: 0x0810 */
176 uint32_t reserved0000[11]; /* address offset: 0x0000 */
177 uint32_t gpio1b_iomux_sel_1; /* address offset: 0x002c */
178 uint32_t gpio1c_iomux_sel_0; /* address offset: 0x0030 */
179 uint32_t gpio1c_iomux_sel_1; /* address offset: 0x0034 */
180 uint32_t gpio1d_iomux_sel_0; /* address offset: 0x0038 */
181 uint32_t gpio1d_iomux_sel_1; /* address offset: 0x003c */
182 uint32_t reserved0040[70]; /* address offset: 0x0040 */
183 uint32_t gpio1b_ds_2; /* address offset: 0x0158 */
184 uint32_t gpio1b_ds_3; /* address offset: 0x015c */
185 uint32_t gpio1c_ds_0; /* address offset: 0x0160 */
186 uint32_t reserved0164[44]; /* address offset: 0x0164 */
187 uint32_t gpio1b_pull; /* address offset: 0x0214 */
188 uint32_t gpio1c_pull; /* address offset: 0x0218 */
189 uint32_t reserved021c[62]; /* address offset: 0x021c */
190 uint32_t gpio1b_ie; /* address offset: 0x0314 */
191 uint32_t gpio1c_ie; /* address offset: 0x0318 */
192 uint32_t reserved031c[62]; /* address offset: 0x031c */
193 uint32_t gpio1b_smt; /* address offset: 0x0414 */
194 uint32_t gpio1c_smt; /* address offset: 0x0418 */
195 uint32_t reserved041c[62]; /* address offset: 0x041c */
196 uint32_t gpio1b_sus; /* address offset: 0x0514 */
197 uint32_t gpio1c_sus; /* address offset: 0x0518 */
198 uint32_t reserved051c[62]; /* address offset: 0x051c */
199 uint32_t gpio1b_sl; /* address offset: 0x0614 */
200 uint32_t gpio1c_sl; /* address offset: 0x0618 */
201 uint32_t reserved061c[62]; /* address offset: 0x061c */
202 uint32_t gpio1b_od; /* address offset: 0x0714 */
203 uint32_t gpio1c_od; /* address offset: 0x0718 */
204 uint32_t reserved071c[58]; /* address offset: 0x071c */
205 uint32_t io_vsel_vccio7; /* address offset: 0x0804 */
206 uint32_t misc_con; /* address offset: 0x0808 */
207 uint32_t sdcard_io_con; /* address offset: 0x080c */
208 uint32_t jtag_m2_con; /* address offset: 0x0810 */