1e1cfe1c9SJoseph Chen /* 2e1cfe1c9SJoseph Chen * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3e1cfe1c9SJoseph Chen * 4e1cfe1c9SJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 5e1cfe1c9SJoseph Chen */ 6e1cfe1c9SJoseph Chen #ifndef _ASM_ARCH_IOC_RK3588_H 7e1cfe1c9SJoseph Chen #define _ASM_ARCH_IOC_RK3588_H 8e1cfe1c9SJoseph Chen 9e1cfe1c9SJoseph Chen #include <common.h> 10e1cfe1c9SJoseph Chen 11e1cfe1c9SJoseph Chen struct rk3588_bus_ioc { 12e1cfe1c9SJoseph Chen uint32_t reserved0000[3]; /* Address Offset: 0x0000 */ 13e1cfe1c9SJoseph Chen uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x000C */ 14e1cfe1c9SJoseph Chen uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */ 15e1cfe1c9SJoseph Chen uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */ 16e1cfe1c9SJoseph Chen uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */ 17e1cfe1c9SJoseph Chen uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x001C */ 18e1cfe1c9SJoseph Chen uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */ 19e1cfe1c9SJoseph Chen uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */ 20e1cfe1c9SJoseph Chen uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */ 21e1cfe1c9SJoseph Chen uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */ 22e1cfe1c9SJoseph Chen uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */ 23e1cfe1c9SJoseph Chen uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */ 24e1cfe1c9SJoseph Chen uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */ 25e1cfe1c9SJoseph Chen uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */ 26e1cfe1c9SJoseph Chen uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */ 27e1cfe1c9SJoseph Chen uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */ 28e1cfe1c9SJoseph Chen uint32_t gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */ 29e1cfe1c9SJoseph Chen uint32_t gpio2b_iomux_sel_h; /* Address Offset: 0x004C */ 30e1cfe1c9SJoseph Chen uint32_t gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */ 31e1cfe1c9SJoseph Chen uint32_t gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */ 32e1cfe1c9SJoseph Chen uint32_t gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */ 33e1cfe1c9SJoseph Chen uint32_t gpio2d_iomux_sel_h; /* Address Offset: 0x005C */ 34e1cfe1c9SJoseph Chen uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */ 35e1cfe1c9SJoseph Chen uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */ 36e1cfe1c9SJoseph Chen uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */ 37e1cfe1c9SJoseph Chen uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */ 38e1cfe1c9SJoseph Chen uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */ 39e1cfe1c9SJoseph Chen uint32_t gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */ 40e1cfe1c9SJoseph Chen uint32_t gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */ 41e1cfe1c9SJoseph Chen uint32_t gpio3d_iomux_sel_h; /* Address Offset: 0x007C */ 42e1cfe1c9SJoseph Chen uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */ 43e1cfe1c9SJoseph Chen uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */ 44e1cfe1c9SJoseph Chen uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */ 45e1cfe1c9SJoseph Chen uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */ 46e1cfe1c9SJoseph Chen uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */ 47e1cfe1c9SJoseph Chen uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */ 48e1cfe1c9SJoseph Chen uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */ 49e1cfe1c9SJoseph Chen uint32_t gpio4d_iomux_sel_h; /* Address Offset: 0x009C */ 50e1cfe1c9SJoseph Chen }; 51e1cfe1c9SJoseph Chen check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C); 52e1cfe1c9SJoseph Chen 53e1cfe1c9SJoseph Chen 54*eebc0615SSteven Liu struct rk3588_pmu1_ioc { 55e1cfe1c9SJoseph Chen uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ 56e1cfe1c9SJoseph Chen uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ 57e1cfe1c9SJoseph Chen uint32_t gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */ 58e1cfe1c9SJoseph Chen uint32_t reserved0012; /* Address Offset: 0x000C */ 59e1cfe1c9SJoseph Chen uint32_t gpio0a_ds_l; /* Address Offset: 0x0010 */ 60e1cfe1c9SJoseph Chen uint32_t gpio0a_ds_h; /* Address Offset: 0x0014 */ 61e1cfe1c9SJoseph Chen uint32_t gpio0b_ds_l; /* Address Offset: 0x0018 */ 62e1cfe1c9SJoseph Chen uint32_t reserved0028; /* Address Offset: 0x001C */ 63e1cfe1c9SJoseph Chen uint32_t gpio0a_p; /* Address Offset: 0x0020 */ 64e1cfe1c9SJoseph Chen uint32_t gpio0b_p; /* Address Offset: 0x0024 */ 65e1cfe1c9SJoseph Chen uint32_t gpio0a_ie; /* Address Offset: 0x0028 */ 66e1cfe1c9SJoseph Chen uint32_t gpio0b_ie; /* Address Offset: 0x002C */ 67e1cfe1c9SJoseph Chen uint32_t gpio0a_smt; /* Address Offset: 0x0030 */ 68e1cfe1c9SJoseph Chen uint32_t gpio0b_smt; /* Address Offset: 0x0034 */ 69e1cfe1c9SJoseph Chen uint32_t gpio0a_pdis; /* Address Offset: 0x0038 */ 70e1cfe1c9SJoseph Chen uint32_t gpio0b_pdis; /* Address Offset: 0x003C */ 71e1cfe1c9SJoseph Chen uint32_t xin_con; /* Address Offset: 0x0040 */ 72e1cfe1c9SJoseph Chen }; 73*eebc0615SSteven Liu check_member(rk3588_pmu1_ioc, xin_con, 0x0040); 74e1cfe1c9SJoseph Chen 75*eebc0615SSteven Liu struct rk3588_pmu2_ioc { 76e1cfe1c9SJoseph Chen uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */ 77e1cfe1c9SJoseph Chen uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */ 78e1cfe1c9SJoseph Chen uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */ 79e1cfe1c9SJoseph Chen uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x000C */ 80e1cfe1c9SJoseph Chen uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */ 81e1cfe1c9SJoseph Chen uint32_t gpio0b_ds_h; /* Address Offset: 0x0014 */ 82e1cfe1c9SJoseph Chen uint32_t gpio0c_ds_l; /* Address Offset: 0x0018 */ 83e1cfe1c9SJoseph Chen uint32_t gpio0c_ds_h; /* Address Offset: 0x001C */ 84e1cfe1c9SJoseph Chen uint32_t gpio0d_ds_l; /* Address Offset: 0x0020 */ 85e1cfe1c9SJoseph Chen uint32_t gpio0d_ds_h; /* Address Offset: 0x0024 */ 86e1cfe1c9SJoseph Chen uint32_t gpio0b_p; /* Address Offset: 0x0028 */ 87e1cfe1c9SJoseph Chen uint32_t gpio0c_p; /* Address Offset: 0x002C */ 88e1cfe1c9SJoseph Chen uint32_t gpio0d_p; /* Address Offset: 0x0030 */ 89e1cfe1c9SJoseph Chen uint32_t gpio0b_ie; /* Address Offset: 0x0034 */ 90e1cfe1c9SJoseph Chen uint32_t gpio0c_ie; /* Address Offset: 0x0038 */ 91e1cfe1c9SJoseph Chen uint32_t gpio0d_ie; /* Address Offset: 0x003C */ 92e1cfe1c9SJoseph Chen uint32_t gpio0b_smt; /* Address Offset: 0x0040 */ 93e1cfe1c9SJoseph Chen uint32_t gpio0c_smt; /* Address Offset: 0x0044 */ 94e1cfe1c9SJoseph Chen uint32_t gpio0d_smt; /* Address Offset: 0x0048 */ 95e1cfe1c9SJoseph Chen uint32_t gpio0b_pdis; /* Address Offset: 0x004C */ 96e1cfe1c9SJoseph Chen uint32_t gpio0c_pdis; /* Address Offset: 0x0050 */ 97e1cfe1c9SJoseph Chen uint32_t gpio0d_pdis; /* Address Offset: 0x0054 */ 98e1cfe1c9SJoseph Chen }; 99*eebc0615SSteven Liu check_member(rk3588_pmu2_ioc, gpio0d_pdis, 0x0054); 100e1cfe1c9SJoseph Chen 101e1cfe1c9SJoseph Chen #endif 102e1cfe1c9SJoseph Chen 103