1*56f7d184SJoseph Chen /* 2*56f7d184SJoseph Chen * (C) Copyright 2022 Rockchip Electronics Co., Ltd. 3*56f7d184SJoseph Chen * 4*56f7d184SJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 5*56f7d184SJoseph Chen */ 6*56f7d184SJoseph Chen #ifndef _ASM_ARCH_GRF_RK3562_H 7*56f7d184SJoseph Chen #define _ASM_ARCH_GRF_RK3562_H 8*56f7d184SJoseph Chen 9*56f7d184SJoseph Chen #include <common.h> 10*56f7d184SJoseph Chen 11*56f7d184SJoseph Chen struct rk3562_pmu_grf { 12*56f7d184SJoseph Chen /* pmugrf */ 13*56f7d184SJoseph Chen uint32_t reserved1[(0x0100 - 0x0000) / 4]; /* address offset: 0x0000 */ 14*56f7d184SJoseph Chen uint32_t soc_con[13]; /* address offset: 0x0100 */ 15*56f7d184SJoseph Chen uint32_t soc_status[1]; /* address offset: 0x0134 */ 16*56f7d184SJoseph Chen uint32_t reserved2[(0x0180 - 0x0134) / 4 - 1]; /* address offset: 0x0138 */ 17*56f7d184SJoseph Chen uint32_t pvtm_con[1]; /* address offset: 0x0180 */ 18*56f7d184SJoseph Chen uint32_t reserved3[(0x0200 - 0x0180) / 4 - 1]; /* address offset: 0x0184 */ 19*56f7d184SJoseph Chen uint32_t os_reg[12]; /* address offset: 0x0200 */ 20*56f7d184SJoseph Chen uint32_t reset_function_status; /* address offset: 0x0230 */ 21*56f7d184SJoseph Chen uint32_t reset_function_clr; /* address offset: 0x0234 */ 22*56f7d184SJoseph Chen uint32_t reserved4[(0x0380 - 0x0234) / 4 - 1]; /* address offset: 0x0238 */ 23*56f7d184SJoseph Chen uint32_t sig_detect_con; /* address offset: 0x0380 */ 24*56f7d184SJoseph Chen uint32_t reserved5[(0x0390 - 0x0380) / 4 - 1]; /* address offset: 0x0384 */ 25*56f7d184SJoseph Chen uint32_t sig_detect_status; /* address offset: 0x0390 */ 26*56f7d184SJoseph Chen uint32_t reserved6[(0x03a0 - 0x0390) / 4 - 1]; /* address offset: 0x0394 */ 27*56f7d184SJoseph Chen uint32_t sig_detect_status_clear; /* address offset: 0x03a0 */ 28*56f7d184SJoseph Chen uint32_t reserved7[(0x03b0 - 0x03a0) / 4 - 1]; /* address offset: 0x03a4 */ 29*56f7d184SJoseph Chen uint32_t sdmmc_det_counter; /* address offset: 0x03b0 */ 30*56f7d184SJoseph Chen }; 31*56f7d184SJoseph Chen 32*56f7d184SJoseph Chen check_member(rk3562_pmu_grf, sdmmc_det_counter, 0x03b0); 33*56f7d184SJoseph Chen 34*56f7d184SJoseph Chen struct rk3562_grf { 35*56f7d184SJoseph Chen /* sysgrf */ 36*56f7d184SJoseph Chen uint32_t reserved1[(0x0400 - 0x0000) / 4]; /* address offset: 0x0000 */ 37*56f7d184SJoseph Chen uint32_t soc_con[7]; /* address offset: 0x0400 */ 38*56f7d184SJoseph Chen uint32_t reserved2[(0x0430 - 0x0400) / 4 - 7]; /* address offset: 0x041c */ 39*56f7d184SJoseph Chen uint32_t soc_status[3]; /* address offset: 0x0430 */ 40*56f7d184SJoseph Chen uint32_t reserved3; /* address offset: 0x043c */ 41*56f7d184SJoseph Chen uint32_t biu_con[2]; /* address offset: 0x0440 */ 42*56f7d184SJoseph Chen uint32_t reserved4[(0x0460 - 0x0440) / 4 - 2]; /* address offset: 0x0448 */ 43*56f7d184SJoseph Chen uint32_t ram_con; /* address offset: 0x0460 */ 44*56f7d184SJoseph Chen uint32_t core_ram_con; /* address offset: 0x0464 */ 45*56f7d184SJoseph Chen uint32_t reserved5[(0x0500 - 0x0464) / 4 - 1]; /* address offset: 0x0468 */ 46*56f7d184SJoseph Chen uint32_t cpu_con[2]; /* address offset: 0x0500 */ 47*56f7d184SJoseph Chen uint32_t reserved6[(0x0510 - 0x0500) / 4 - 2]; /* address offset: 0x0508 */ 48*56f7d184SJoseph Chen uint32_t cpu_status[2]; /* address offset: 0x0510 */ 49*56f7d184SJoseph Chen uint32_t reserved7[(0x0520 - 0x0510) / 4 - 2]; /* address offset: 0x0518 */ 50*56f7d184SJoseph Chen uint32_t vi_con[2]; /* address offset: 0x0520 */ 51*56f7d184SJoseph Chen uint32_t reserved8[(0x0530 - 0x0520) / 4 - 2]; /* address offset: 0x0528 */ 52*56f7d184SJoseph Chen uint32_t vi_status[1]; /* address offset: 0x0530 */ 53*56f7d184SJoseph Chen uint32_t reserved9[(0x0570 - 0x0530) / 4 - 1]; /* address offset: 0x0534 */ 54*56f7d184SJoseph Chen uint32_t gpu_con[2]; /* address offset: 0x0570 */ 55*56f7d184SJoseph Chen uint32_t reserved10[(0x0580 - 0x0570) / 4 - 2]; /* address offset: 0x0578 */ 56*56f7d184SJoseph Chen uint32_t tsadc_con; /* address offset: 0x0580 */ 57*56f7d184SJoseph Chen uint32_t reserved11[(0x05d0 - 0x0580) / 4 - 1]; /* address offset: 0x0584 */ 58*56f7d184SJoseph Chen uint32_t vo_con[2]; /* address offset: 0x05d0 */ 59*56f7d184SJoseph Chen uint32_t reserved12[(0x0600 - 0x05d0) / 4 - 2]; /* address offset: 0x05d8 */ 60*56f7d184SJoseph Chen uint32_t top_pvtpll_con[4]; /* address offset: 0x0600 */ 61*56f7d184SJoseph Chen uint32_t top_pvtpll_status[2]; /* address offset: 0x0610 */ 62*56f7d184SJoseph Chen uint32_t reserved13[(0x0620 - 0x0610) / 4 - 2]; /* address offset: 0x0618 */ 63*56f7d184SJoseph Chen uint32_t cpu_pvtpll_con[4]; /* address offset: 0x0620 */ 64*56f7d184SJoseph Chen uint32_t cpu_pvtpll_status[2]; /* address offset: 0x0630 */ 65*56f7d184SJoseph Chen uint32_t reserved14[(0x0640 - 0x0630) / 4 - 2]; /* address offset: 0x0638 */ 66*56f7d184SJoseph Chen uint32_t gpu_pvtpll_con[4]; /* address offset: 0x0640 */ 67*56f7d184SJoseph Chen uint32_t gpu_pvtpll_status[2]; /* address offset: 0x0650 */ 68*56f7d184SJoseph Chen uint32_t reserved15[(0x0660 - 0x0650) / 4 - 2]; /* address offset: 0x0658 */ 69*56f7d184SJoseph Chen uint32_t npu_pvtpll_con[4]; /* address offset: 0x0660 */ 70*56f7d184SJoseph Chen uint32_t npu_pvtpll_status[2]; /* address offset: 0x0670 */ 71*56f7d184SJoseph Chen uint32_t reserved16[(0x0800 - 0x0670) / 4 - 2]; /* address offset: 0x0678 */ 72*56f7d184SJoseph Chen uint32_t chip_id; /* address offset: 0x0800 */ 73*56f7d184SJoseph Chen }; 74*56f7d184SJoseph Chen check_member(rk3562_grf, chip_id, 0x0800); 75*56f7d184SJoseph Chen 76*56f7d184SJoseph Chen #endif 77