1c6f7c1a3SJoseph Chen /* 2c6f7c1a3SJoseph Chen * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3c6f7c1a3SJoseph Chen * 4c6f7c1a3SJoseph Chen * SPDX-License-Identifier: GPL-2.0+ 5c6f7c1a3SJoseph Chen */ 6*6dbcf66bSJoseph Chen #ifndef _ASM_ARCH_IOC_RK3528_H 7*6dbcf66bSJoseph Chen #define _ASM_ARCH_IOC_RK3528_H 8c6f7c1a3SJoseph Chen 9c6f7c1a3SJoseph Chen #include <common.h> 10c6f7c1a3SJoseph Chen 11c6f7c1a3SJoseph Chen struct rk3528_gpio0_ioc { 12c6f7c1a3SJoseph Chen uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ 13c6f7c1a3SJoseph Chen uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ 14c6f7c1a3SJoseph Chen uint32_t reserved0008[62]; /* Address Offset: 0x0008 */ 15c6f7c1a3SJoseph Chen uint32_t gpio0a_ds[3]; /* Address Offset: 0x0100 */ 16c6f7c1a3SJoseph Chen uint32_t reserved010c[61]; /* Address Offset: 0x010C */ 17c6f7c1a3SJoseph Chen uint32_t gpio0a_pull; /* Address Offset: 0x0200 */ 18c6f7c1a3SJoseph Chen uint32_t reserved0204[63]; /* Address Offset: 0x0204 */ 19c6f7c1a3SJoseph Chen uint32_t gpio0a_ie; /* Address Offset: 0x0300 */ 20c6f7c1a3SJoseph Chen uint32_t reserved0304[63]; /* Address Offset: 0x0304 */ 21c6f7c1a3SJoseph Chen uint32_t gpio0a_smt; /* Address Offset: 0x0400 */ 22c6f7c1a3SJoseph Chen uint32_t reserved0404[63]; /* Address Offset: 0x0404 */ 23c6f7c1a3SJoseph Chen uint32_t gpio0a_sus; /* Address Offset: 0x0500 */ 24c6f7c1a3SJoseph Chen uint32_t reserved0504[63]; /* Address Offset: 0x0504 */ 25c6f7c1a3SJoseph Chen uint32_t gpio0a_sl; /* Address Offset: 0x0600 */ 26c6f7c1a3SJoseph Chen uint32_t reserved0604[63]; /* Address Offset: 0x0604 */ 27c6f7c1a3SJoseph Chen uint32_t gpio0a_od; /* Address Offset: 0x0700 */ 28c6f7c1a3SJoseph Chen uint32_t vcc5vio_ctrl; /* Address Offset: 0x0704 */ 29c6f7c1a3SJoseph Chen }; 30c6f7c1a3SJoseph Chen check_member(rk3528_gpio0_ioc, vcc5vio_ctrl, 0x0704); 31c6f7c1a3SJoseph Chen 32c6f7c1a3SJoseph Chen struct rk3528_gpio1_ioc { 33c6f7c1a3SJoseph Chen uint32_t reserved0000[8]; /* Address Offset: 0x0000 */ 34c6f7c1a3SJoseph Chen uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */ 35c6f7c1a3SJoseph Chen uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */ 36c6f7c1a3SJoseph Chen uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */ 37c6f7c1a3SJoseph Chen uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */ 38c6f7c1a3SJoseph Chen uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */ 39c6f7c1a3SJoseph Chen uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */ 40c6f7c1a3SJoseph Chen uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */ 41c6f7c1a3SJoseph Chen uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */ 42c6f7c1a3SJoseph Chen uint32_t reserved0040[56]; /* Address Offset: 0x0040 */ 43c6f7c1a3SJoseph Chen uint32_t gpio1a_ds[4]; /* Address Offset: 0x0120 */ 44c6f7c1a3SJoseph Chen uint32_t gpio1b_ds[4]; /* Address Offset: 0x0130 */ 45c6f7c1a3SJoseph Chen uint32_t gpio1c_ds[4]; /* Address Offset: 0x0140 */ 46c6f7c1a3SJoseph Chen uint32_t gpio1d_ds[4]; /* Address Offset: 0x0150 */ 47c6f7c1a3SJoseph Chen uint32_t reserved0160[44]; /* Address Offset: 0x0160 */ 48c6f7c1a3SJoseph Chen uint32_t gpio1a_pull; /* Address Offset: 0x0210 */ 49c6f7c1a3SJoseph Chen uint32_t gpio1b_pull; /* Address Offset: 0x0214 */ 50c6f7c1a3SJoseph Chen uint32_t gpio1c_pull; /* Address Offset: 0x0218 */ 51c6f7c1a3SJoseph Chen uint32_t gpio1d_pull; /* Address Offset: 0x021C */ 52c6f7c1a3SJoseph Chen uint32_t reserved0220[60]; /* Address Offset: 0x0220 */ 53c6f7c1a3SJoseph Chen uint32_t gpio1a_ie; /* Address Offset: 0x0310 */ 54c6f7c1a3SJoseph Chen uint32_t gpio1b_ie; /* Address Offset: 0x0314 */ 55c6f7c1a3SJoseph Chen uint32_t gpio1c_ie; /* Address Offset: 0x0318 */ 56c6f7c1a3SJoseph Chen uint32_t gpio1d_ie; /* Address Offset: 0x031C */ 57c6f7c1a3SJoseph Chen uint32_t reserved0320[60]; /* Address Offset: 0x0320 */ 58c6f7c1a3SJoseph Chen uint32_t gpio1a_smt; /* Address Offset: 0x0410 */ 59c6f7c1a3SJoseph Chen uint32_t gpio1b_smt; /* Address Offset: 0x0414 */ 60c6f7c1a3SJoseph Chen uint32_t gpio1c_smt; /* Address Offset: 0x0418 */ 61c6f7c1a3SJoseph Chen uint32_t gpio1d_smt; /* Address Offset: 0x041C */ 62c6f7c1a3SJoseph Chen uint32_t reserved0420[60]; /* Address Offset: 0x0420 */ 63c6f7c1a3SJoseph Chen uint32_t gpio1a_sus; /* Address Offset: 0x0510 */ 64c6f7c1a3SJoseph Chen uint32_t gpio1b_sus; /* Address Offset: 0x0514 */ 65c6f7c1a3SJoseph Chen uint32_t gpio1c_sus; /* Address Offset: 0x0518 */ 66c6f7c1a3SJoseph Chen uint32_t gpio1d_sus; /* Address Offset: 0x051C */ 67c6f7c1a3SJoseph Chen uint32_t reserved0520[60]; /* Address Offset: 0x0520 */ 68c6f7c1a3SJoseph Chen uint32_t gpio1a_sl; /* Address Offset: 0x0610 */ 69c6f7c1a3SJoseph Chen uint32_t gpio1b_sl; /* Address Offset: 0x0614 */ 70c6f7c1a3SJoseph Chen uint32_t gpio1c_sl; /* Address Offset: 0x0618 */ 71c6f7c1a3SJoseph Chen uint32_t gpio1d_sl; /* Address Offset: 0x061C */ 72c6f7c1a3SJoseph Chen uint32_t reserved0620[60]; /* Address Offset: 0x0620 */ 73c6f7c1a3SJoseph Chen uint32_t gpio1a_od; /* Address Offset: 0x0710 */ 74c6f7c1a3SJoseph Chen uint32_t gpio1b_od; /* Address Offset: 0x0714 */ 75c6f7c1a3SJoseph Chen uint32_t gpio1c_od; /* Address Offset: 0x0718 */ 76c6f7c1a3SJoseph Chen uint32_t gpio1d_od; /* Address Offset: 0x071C */ 77c6f7c1a3SJoseph Chen uint32_t reserved0720[60]; /* Address Offset: 0x0720 */ 78c6f7c1a3SJoseph Chen uint32_t vccio0_poc; /* Address Offset: 0x0810 */ 79c6f7c1a3SJoseph Chen uint32_t reserved0814[3]; /* Address Offset: 0x0814 */ 80c6f7c1a3SJoseph Chen uint32_t vccio1_poc; /* Address Offset: 0x0820 */ 81c6f7c1a3SJoseph Chen }; 82c6f7c1a3SJoseph Chen check_member(rk3528_gpio1_ioc, vccio1_poc, 0x0820); 83c6f7c1a3SJoseph Chen 84c6f7c1a3SJoseph Chen struct rk3528_gpio2_ioc { 85c6f7c1a3SJoseph Chen uint32_t reserved0000[16]; /* Address Offset: 0x0000 */ 86c6f7c1a3SJoseph Chen uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */ 87c6f7c1a3SJoseph Chen uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */ 88c6f7c1a3SJoseph Chen uint32_t reserved0048[70]; /* Address Offset: 0x0048 */ 89c6f7c1a3SJoseph Chen uint32_t gpio2a_ds[4]; /* Address Offset: 0x0160 */ 90c6f7c1a3SJoseph Chen uint32_t reserved0170[44]; /* Address Offset: 0x0170 */ 91c6f7c1a3SJoseph Chen uint32_t gpio2a_pull; /* Address Offset: 0x0220 */ 92c6f7c1a3SJoseph Chen uint32_t reserved0224[63]; /* Address Offset: 0x0224 */ 93c6f7c1a3SJoseph Chen uint32_t gpio2a_ie; /* Address Offset: 0x0320 */ 94c6f7c1a3SJoseph Chen uint32_t reserved0324[63]; /* Address Offset: 0x0324 */ 95c6f7c1a3SJoseph Chen uint32_t gpio2a_smt; /* Address Offset: 0x0420 */ 96c6f7c1a3SJoseph Chen uint32_t reserved0424[63]; /* Address Offset: 0x0424 */ 97c6f7c1a3SJoseph Chen uint32_t gpio2a_sus; /* Address Offset: 0x0520 */ 98c6f7c1a3SJoseph Chen uint32_t reserved0524[63]; /* Address Offset: 0x0524 */ 99c6f7c1a3SJoseph Chen uint32_t gpio2a_sl; /* Address Offset: 0x0620 */ 100c6f7c1a3SJoseph Chen uint32_t reserved0624[63]; /* Address Offset: 0x0624 */ 101c6f7c1a3SJoseph Chen uint32_t gpio2a_od; /* Address Offset: 0x0720 */ 102c6f7c1a3SJoseph Chen uint32_t reserved0724[67]; /* Address Offset: 0x0724 */ 103c6f7c1a3SJoseph Chen uint32_t vccio2_poc; /* Address Offset: 0x0830 */ 104c6f7c1a3SJoseph Chen }; 105c6f7c1a3SJoseph Chen check_member(rk3528_gpio2_ioc, vccio2_poc, 0x0830); 106c6f7c1a3SJoseph Chen 107c6f7c1a3SJoseph Chen struct rk3528_gpio3_ioc { 108c6f7c1a3SJoseph Chen uint32_t reserved0000[24]; /* Address Offset: 0x0000 */ 109c6f7c1a3SJoseph Chen uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */ 110c6f7c1a3SJoseph Chen uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */ 111c6f7c1a3SJoseph Chen uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */ 112c6f7c1a3SJoseph Chen uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */ 113c6f7c1a3SJoseph Chen uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */ 114c6f7c1a3SJoseph Chen uint32_t reserved0074[71]; /* Address Offset: 0x0074 */ 115c6f7c1a3SJoseph Chen uint32_t gpio3a_ds[4]; /* Address Offset: 0x0190 */ 116c6f7c1a3SJoseph Chen uint32_t gpio3b_ds[4]; /* Address Offset: 0x01A0 */ 117c6f7c1a3SJoseph Chen uint32_t gpio3c_ds[2]; /* Address Offset: 0x01B0 */ 118c6f7c1a3SJoseph Chen uint32_t reserved01b8[30]; /* Address Offset: 0x01B8 */ 119c6f7c1a3SJoseph Chen uint32_t gpio3a_pull; /* Address Offset: 0x0230 */ 120c6f7c1a3SJoseph Chen uint32_t gpio3b_pull; /* Address Offset: 0x0234 */ 121c6f7c1a3SJoseph Chen uint32_t gpio3c_pull; /* Address Offset: 0x0238 */ 122c6f7c1a3SJoseph Chen uint32_t reserved023c[61]; /* Address Offset: 0x023C */ 123c6f7c1a3SJoseph Chen uint32_t gpio3a_ie; /* Address Offset: 0x0330 */ 124c6f7c1a3SJoseph Chen uint32_t gpio3b_ie; /* Address Offset: 0x0334 */ 125c6f7c1a3SJoseph Chen uint32_t gpio3c_ie; /* Address Offset: 0x0338 */ 126c6f7c1a3SJoseph Chen uint32_t reserved033c[61]; /* Address Offset: 0x033C */ 127c6f7c1a3SJoseph Chen uint32_t gpio3a_smt; /* Address Offset: 0x0430 */ 128c6f7c1a3SJoseph Chen uint32_t gpio3b_smt; /* Address Offset: 0x0434 */ 129c6f7c1a3SJoseph Chen uint32_t gpio3c_smt; /* Address Offset: 0x0438 */ 130c6f7c1a3SJoseph Chen uint32_t reserved043c[61]; /* Address Offset: 0x043C */ 131c6f7c1a3SJoseph Chen uint32_t gpio3a_sus; /* Address Offset: 0x0530 */ 132c6f7c1a3SJoseph Chen uint32_t gpio3b_sus; /* Address Offset: 0x0534 */ 133c6f7c1a3SJoseph Chen uint32_t gpio3c_sus; /* Address Offset: 0x0538 */ 134c6f7c1a3SJoseph Chen uint32_t reserved053c[61]; /* Address Offset: 0x053C */ 135c6f7c1a3SJoseph Chen uint32_t gpio3a_sl; /* Address Offset: 0x0630 */ 136c6f7c1a3SJoseph Chen uint32_t gpio3b_sl; /* Address Offset: 0x0634 */ 137c6f7c1a3SJoseph Chen uint32_t gpio3c_sl; /* Address Offset: 0x0638 */ 138c6f7c1a3SJoseph Chen uint32_t reserved063c[61]; /* Address Offset: 0x063C */ 139c6f7c1a3SJoseph Chen uint32_t gpio3a_od; /* Address Offset: 0x0730 */ 140c6f7c1a3SJoseph Chen uint32_t gpio3b_od; /* Address Offset: 0x0734 */ 141c6f7c1a3SJoseph Chen uint32_t gpio3c_od; /* Address Offset: 0x0738 */ 142c6f7c1a3SJoseph Chen uint32_t reserved073c[65]; /* Address Offset: 0x073C */ 143c6f7c1a3SJoseph Chen uint32_t vccio3_poc; /* Address Offset: 0x0840 */ 144c6f7c1a3SJoseph Chen }; 145c6f7c1a3SJoseph Chen check_member(rk3528_gpio3_ioc, vccio3_poc, 0x0840); 146c6f7c1a3SJoseph Chen 147c6f7c1a3SJoseph Chen struct rk3528_gpio4_ioc { 148c6f7c1a3SJoseph Chen uint32_t reserved0000[32]; /* Address Offset: 0x0000 */ 149c6f7c1a3SJoseph Chen uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */ 150c6f7c1a3SJoseph Chen uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */ 151c6f7c1a3SJoseph Chen uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */ 152c6f7c1a3SJoseph Chen uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */ 153c6f7c1a3SJoseph Chen uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */ 154c6f7c1a3SJoseph Chen uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */ 155c6f7c1a3SJoseph Chen uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */ 156c6f7c1a3SJoseph Chen uint32_t reserved009c[73]; /* Address Offset: 0x009C */ 157c6f7c1a3SJoseph Chen uint32_t gpio4a_ds[4]; /* Address Offset: 0x01C0 */ 158c6f7c1a3SJoseph Chen uint32_t gpio4b_ds[4]; /* Address Offset: 0x01D0 */ 159c6f7c1a3SJoseph Chen uint32_t gpio4c_ds[4]; /* Address Offset: 0x01E0 */ 160c6f7c1a3SJoseph Chen uint32_t gpio4d_ds[1]; /* Address Offset: 0x01F0 */ 161c6f7c1a3SJoseph Chen uint32_t reserved01f4[19]; /* Address Offset: 0x01F4 */ 162c6f7c1a3SJoseph Chen uint32_t gpio4a_pull; /* Address Offset: 0x0240 */ 163c6f7c1a3SJoseph Chen uint32_t gpio4b_pull; /* Address Offset: 0x0244 */ 164c6f7c1a3SJoseph Chen uint32_t gpio4c_pull; /* Address Offset: 0x0248 */ 165c6f7c1a3SJoseph Chen uint32_t gpio4d_pull; /* Address Offset: 0x024C */ 166c6f7c1a3SJoseph Chen uint32_t reserved0250[60]; /* Address Offset: 0x0250 */ 167c6f7c1a3SJoseph Chen uint32_t gpio4a_ie; /* Address Offset: 0x0340 */ 168c6f7c1a3SJoseph Chen uint32_t gpio4b_ie; /* Address Offset: 0x0344 */ 169c6f7c1a3SJoseph Chen uint32_t gpio4c_ie; /* Address Offset: 0x0348 */ 170c6f7c1a3SJoseph Chen uint32_t gpio4d_ie; /* Address Offset: 0x034C */ 171c6f7c1a3SJoseph Chen uint32_t reserved0350[60]; /* Address Offset: 0x0350 */ 172c6f7c1a3SJoseph Chen uint32_t gpio4a_smt; /* Address Offset: 0x0440 */ 173c6f7c1a3SJoseph Chen uint32_t gpio4b_smt; /* Address Offset: 0x0444 */ 174c6f7c1a3SJoseph Chen uint32_t gpio4c_smt; /* Address Offset: 0x0448 */ 175c6f7c1a3SJoseph Chen uint32_t gpio4d_smt; /* Address Offset: 0x044C */ 176c6f7c1a3SJoseph Chen uint32_t reserved0450[60]; /* Address Offset: 0x0450 */ 177c6f7c1a3SJoseph Chen uint32_t gpio4a_sus; /* Address Offset: 0x0540 */ 178c6f7c1a3SJoseph Chen uint32_t gpio4b_sus; /* Address Offset: 0x0544 */ 179c6f7c1a3SJoseph Chen uint32_t gpio4c_sus; /* Address Offset: 0x0548 */ 180c6f7c1a3SJoseph Chen uint32_t gpio4d_sus; /* Address Offset: 0x054C */ 181c6f7c1a3SJoseph Chen uint32_t reserved0550[60]; /* Address Offset: 0x0550 */ 182c6f7c1a3SJoseph Chen uint32_t gpio4a_sl; /* Address Offset: 0x0640 */ 183c6f7c1a3SJoseph Chen uint32_t gpio4b_sl; /* Address Offset: 0x0644 */ 184c6f7c1a3SJoseph Chen uint32_t gpio4c_sl; /* Address Offset: 0x0648 */ 185c6f7c1a3SJoseph Chen uint32_t gpio4d_sl; /* Address Offset: 0x064C */ 186c6f7c1a3SJoseph Chen uint32_t reserved0650[60]; /* Address Offset: 0x0650 */ 187c6f7c1a3SJoseph Chen uint32_t gpio4a_od; /* Address Offset: 0x0740 */ 188c6f7c1a3SJoseph Chen uint32_t gpio4b_od; /* Address Offset: 0x0744 */ 189c6f7c1a3SJoseph Chen uint32_t gpio4c_od; /* Address Offset: 0x0748 */ 190c6f7c1a3SJoseph Chen uint32_t gpio4d_od; /* Address Offset: 0x074C */ 191c6f7c1a3SJoseph Chen uint32_t reserved0750[64]; /* Address Offset: 0x0750 */ 192c6f7c1a3SJoseph Chen uint32_t vccio4_poc; /* Address Offset: 0x0850 */ 193c6f7c1a3SJoseph Chen }; 194c6f7c1a3SJoseph Chen check_member(rk3528_gpio4_ioc, vccio4_poc, 0x0850); 195c6f7c1a3SJoseph Chen #endif 196c6f7c1a3SJoseph Chen 197