Lines Matching refs:uint32_t
17 uint32_t CLK_CTL; /* Address Offset: 0x0000 */
18 uint32_t RST_CTL; /* Address Offset: 0x0004 */
19 uint32_t RESERVED0008[126]; /* Address Offset: 0x0008 */
20 uint32_t TD_ADDR; /* Address Offset: 0x0200 */
21 uint32_t TD_LOAD_CTRL; /* Address Offset: 0x0204 */
22 uint32_t FIFO_ST; /* Address Offset: 0x0208 */
23 uint32_t RESERVED020C; /* Address Offset: 0x020C */
24 uint32_t SYMM_INT_EN; /* Address Offset: 0x0210 */
25 uint32_t SYMM_INT_ST; /* Address Offset: 0x0214 */
26 uint32_t SYMM_TD_ID; /* Address Offset: 0x0218 */
27 uint32_t SYMM_TD_ST; /* Address Offset: 0x021C */
28 uint32_t SYMM_ST_DBG; /* Address Offset: 0x0220 */
29 uint32_t SYMM_CONTEXT_SIZE; /* Address Offset: 0x0224 */
30 uint32_t SYMM_TD_ADDR_DBG; /* Address Offset: 0x0228 */
31 uint32_t SYMM_TD_GRANT_DBG; /* Address Offset: 0x022C */
32 uint32_t HASH_INT_EN; /* Address Offset: 0x0230 */
33 uint32_t HASH_INT_ST; /* Address Offset: 0x0234 */
34 uint32_t HASH_TD_ID; /* Address Offset: 0x0238 */
35 uint32_t HASH_TD_ST; /* Address Offset: 0x023C */
36 uint32_t HASH_ST_DBG; /* Address Offset: 0x0240 */
37 uint32_t HASH_CONTEXT_SIZE; /* Address Offset: 0x0244 */
38 uint32_t HASH_TD_ADDR_DBG; /* Address Offset: 0x0248 */
39 uint32_t HASH_TD_GRANT_DBG; /* Address Offset: 0x024C */
40 uint32_t SYMM_TD_POP_ADDR; /* Address Offset: 0x0250 */
41 uint32_t HASH_TD_POP_ADDR; /* Address Offset: 0x0254 */
42 uint32_t TD_POP_CTRL; /* Address Offset: 0x0258 */
43 uint32_t RESERVED025C[5]; /* Address Offset: 0x025C */
44 uint32_t KL_TO_CE_PADDR; /* Address Offset: 0x0270 */
45 uint32_t KL_KD_ADDR; /* Address Offset: 0x0274 */
46 uint32_t RESERVED0278[94]; /* Address Offset: 0x0278 */
47 uint32_t ECC_CTL; /* Address Offset: 0x03F0 */
48 uint32_t ECC_INT_EN; /* Address Offset: 0x03F4 */
49 uint32_t ECC_INT_ST; /* Address Offset: 0x03F8 */
50 uint32_t ECC_ABN_ST; /* Address Offset: 0x03FC */
51 uint32_t ECC_CURVE_WIDE; /* Address Offset: 0x0400 */
52 uint32_t ECC_MAX_CURVE_WIDE; /* Address Offset: 0x0404 */
53 uint32_t ECC_DATA_ENDIAN; /* Address Offset: 0x0408 */
54 uint32_t RESERVED040C[17]; /* Address Offset: 0x040C */
55 uint32_t KL_APB_CMD; /* Address Offset: 0x0450 */
56 uint32_t KL_APB_PADDR; /* Address Offset: 0x0454 */
57 uint32_t KL_APB_PWDATA; /* Address Offset: 0x0458 */
58 uint32_t RESERVED045C[2]; /* Address Offset: 0x045C */
59 uint32_t KL_KD_VID; /* Address Offset: 0x0464 */
60 uint32_t KL_KD_MODE; /* Address Offset: 0x0468 */
61 uint32_t RESERVED046C[5]; /* Address Offset: 0x046C */
62 uint32_t PKA_RAM_CTL; /* Address Offset: 0x0480 */
63 uint32_t PKA_RAM_ST; /* Address Offset: 0x0484 */
64 uint32_t RESERVED0488[6]; /* Address Offset: 0x0488 */
65 uint32_t PKA_DEBUG_CTL; /* Address Offset: 0x04A0 */
66 uint32_t PKA_DEBUG_ST; /* Address Offset: 0x04A4 */
67 uint32_t PKA_DEBUG_MONITOR; /* Address Offset: 0x04A8 */
68 uint32_t RESERVED04AC[85]; /* Address Offset: 0x04AC */
69 uint32_t KT_ST; /* Address Offset: 0x0600 */
70 uint32_t RESERVED0604; /* Address Offset: 0x0604 */
71 uint32_t KL_INTER_COPY; /* Address Offset: 0x0608 */
72 uint32_t RESERVED060C[4]; /* Address Offset: 0x060C */
73 uint32_t LOCKSTEP_EN; /* Address Offset: 0x061C */
74 uint32_t RESERVED0620[2]; /* Address Offset: 0x0620 */
75 uint32_t LOCKSTEP_IJERR; /* Address Offset: 0x0628 */
76 uint32_t RESERVED062C[5]; /* Address Offset: 0x062C */
77 uint32_t KL_OTP_KEY_REQ; /* Address Offset: 0x0640 */
78 uint32_t KL_KEY_CLEAR; /* Address Offset: 0x0644 */
79 uint32_t KL_OTP_KEY_LEN; /* Address Offset: 0x0648 */
80 uint32_t KL_HW_DRNG_REQ; /* Address Offset: 0x064C */
81 uint32_t RESERVED0650[12]; /* Address Offset: 0x0650 */
82 uint32_t AES_VER; /* Address Offset: 0x0680 */
83 uint32_t DES_VER; /* Address Offset: 0x0684 */
84 uint32_t SM4_VER; /* Address Offset: 0x0688 */
85 uint32_t HASH_VER; /* Address Offset: 0x068C */
86 uint32_t HMAC_VER; /* Address Offset: 0x0690 */
87 uint32_t RESERVED0694; /* Address Offset: 0x0694 */
88 uint32_t PKA_VER; /* Address Offset: 0x0698 */
89 uint32_t EXTRA_FEATURE; /* Address Offset: 0x069C */
90 uint32_t RESERVED06A0[20]; /* Address Offset: 0x06A0 */
91 uint32_t CE_VER; /* Address Offset: 0x06F0 */
92 uint32_t RESERVED06F4[67]; /* Address Offset: 0x06F4 */
93 uint32_t PKA_MEM_MAP0; /* Address Offset: 0x0800 */
94 uint32_t PKA_MEM_MAP1; /* Address Offset: 0x0804 */
95 uint32_t PKA_MEM_MAP2; /* Address Offset: 0x0808 */
96 uint32_t PKA_MEM_MAP3; /* Address Offset: 0x080C */
97 uint32_t PKA_MEM_MAP4; /* Address Offset: 0x0810 */
98 uint32_t PKA_MEM_MAP5; /* Address Offset: 0x0814 */
99 uint32_t PKA_MEM_MAP6; /* Address Offset: 0x0818 */
100 uint32_t PKA_MEM_MAP7; /* Address Offset: 0x081C */
101 uint32_t PKA_MEM_MAP8; /* Address Offset: 0x0820 */
102 uint32_t PKA_MEM_MAP9; /* Address Offset: 0x0824 */
103 uint32_t PKA_MEM_MAP10; /* Address Offset: 0x0828 */
104 uint32_t PKA_MEM_MAP11; /* Address Offset: 0x082C */
105 uint32_t PKA_MEM_MAP12; /* Address Offset: 0x0830 */
106 uint32_t PKA_MEM_MAP13; /* Address Offset: 0x0834 */
107 uint32_t PKA_MEM_MAP14; /* Address Offset: 0x0838 */
108 uint32_t PKA_MEM_MAP15; /* Address Offset: 0x083C */
109 uint32_t PKA_MEM_MAP16; /* Address Offset: 0x0840 */
110 uint32_t PKA_MEM_MAP17; /* Address Offset: 0x0844 */
111 uint32_t PKA_MEM_MAP18; /* Address Offset: 0x0848 */
112 uint32_t PKA_MEM_MAP19; /* Address Offset: 0x084C */
113 uint32_t PKA_MEM_MAP20; /* Address Offset: 0x0850 */
114 uint32_t PKA_MEM_MAP21; /* Address Offset: 0x0854 */
115 uint32_t PKA_MEM_MAP22; /* Address Offset: 0x0858 */
116 uint32_t PKA_MEM_MAP23; /* Address Offset: 0x085C */
117 uint32_t PKA_MEM_MAP24; /* Address Offset: 0x0860 */
118 uint32_t PKA_MEM_MAP25; /* Address Offset: 0x0864 */
119 uint32_t PKA_MEM_MAP26; /* Address Offset: 0x0868 */
120 uint32_t PKA_MEM_MAP27; /* Address Offset: 0x086C */
121 uint32_t PKA_MEM_MAP28; /* Address Offset: 0x0870 */
122 uint32_t PKA_MEM_MAP29; /* Address Offset: 0x0874 */
123 uint32_t PKA_MEM_MAP30; /* Address Offset: 0x0878 */
124 uint32_t PKA_MEM_MAP31; /* Address Offset: 0x087C */
125 uint32_t PKA_OPCODE; /* Address Offset: 0x0880 */
126 uint32_t N_NP_T0_T1_ADDR; /* Address Offset: 0x0884 */
127 uint32_t PKA_STATUS; /* Address Offset: 0x0888 */
128 uint32_t RESERVED088C; /* Address Offset: 0x088C */
129 uint32_t PKA_L0; /* Address Offset: 0x0890 */
130 uint32_t PKA_L1; /* Address Offset: 0x0894 */
131 uint32_t PKA_L2; /* Address Offset: 0x0898 */
132 uint32_t PKA_L3; /* Address Offset: 0x089C */
133 uint32_t PKA_L4; /* Address Offset: 0x08A0 */
134 uint32_t PKA_L5; /* Address Offset: 0x08A4 */
135 uint32_t PKA_L6; /* Address Offset: 0x08A8 */
136 uint32_t PKA_L7; /* Address Offset: 0x08AC */
137 uint32_t PKA_PIPE_RDY; /* Address Offset: 0x08B0 */
138 uint32_t PKA_DONE; /* Address Offset: 0x08B4 */
139 uint32_t PKA_MON_SELECT; /* Address Offset: 0x08B8 */
140 uint32_t PKA_DEBUG_REG_EN; /* Address Offset: 0x08BC */
141 uint32_t DEBUG_CNT_ADDR; /* Address Offset: 0x08C0 */
142 uint32_t DEBUG_EXT_ADDR; /* Address Offset: 0x08C4 */
143 uint32_t PKA_DEBUG_HALT; /* Address Offset: 0x08C8 */
144 uint32_t RESERVED08CC; /* Address Offset: 0x08CC */
145 uint32_t PKA_MON_READ; /* Address Offset: 0x08D0 */
146 uint32_t PKA_INT_ENA; /* Address Offset: 0x08D4 */
147 uint32_t PKA_INT_ST; /* Address Offset: 0x08D8 */
148 uint32_t TD0_TD1_TX_ADDR; /* Address Offset: 0x08DC */
149 uint32_t RESERVED08E0[456]; /* Address Offset: 0x08E0 */
150 uint32_t SRAM_ADDR; /* Address Offset: 0x1000 */