Lines Matching refs:uint32_t
13 uint32_t con0; /* address offset: 0x0000 */
14 uint32_t con1; /* address offset: 0x0004 */
15 uint32_t mem_cfg_uhdspra; /* address offset: 0x0008 */
16 uint32_t status0; /* address offset: 0x000c */
17 uint32_t status1; /* address offset: 0x0010 */
24 uint32_t con0; /* address offset: 0x0000 */
25 uint32_t con1; /* address offset: 0x0004 */
26 uint32_t reserved0008[2]; /* address offset: 0x0008 */
27 uint32_t con4; /* address offset: 0x0010 */
28 uint32_t reserved0014[7]; /* address offset: 0x0014 */
29 uint32_t con12; /* address offset: 0x0030 */
30 uint32_t con13; /* address offset: 0x0034 */
31 uint32_t con14; /* address offset: 0x0038 */
32 uint32_t con15; /* address offset: 0x003c */
33 uint32_t con16; /* address offset: 0x0040 */
34 uint32_t con17; /* address offset: 0x0044 */
35 uint32_t con18; /* address offset: 0x0048 */
36 uint32_t reserved004c; /* address offset: 0x004c */
37 uint32_t con20; /* address offset: 0x0050 */
38 uint32_t con21; /* address offset: 0x0054 */
39 uint32_t con22; /* address offset: 0x0058 */
40 uint32_t con23; /* address offset: 0x005c */
41 uint32_t reserved0060[8]; /* address offset: 0x0060 */
42 uint32_t probe_ctrl; /* address offset: 0x0080 */
43 uint32_t reserved0084[31]; /* address offset: 0x0084 */
44 uint32_t status0; /* address offset: 0x0100 */
45 uint32_t status1; /* address offset: 0x0104 */
46 uint32_t status2; /* address offset: 0x0108 */
47 uint32_t status3; /* address offset: 0x010c */
48 uint32_t status4; /* address offset: 0x0110 */
49 uint32_t status5; /* address offset: 0x0114 */
50 uint32_t status6; /* address offset: 0x0118 */
51 uint32_t status7; /* address offset: 0x011c */
52 uint32_t status8; /* address offset: 0x0120 */
53 uint32_t status9; /* address offset: 0x0124 */
54 uint32_t status10; /* address offset: 0x0128 */
55 uint32_t status11; /* address offset: 0x012c */
56 uint32_t status12; /* address offset: 0x0130 */
57 uint32_t status13; /* address offset: 0x0134 */
58 uint32_t status14; /* address offset: 0x0138 */
59 uint32_t status15; /* address offset: 0x013c */
60 uint32_t status16; /* address offset: 0x0140 */
61 uint32_t status17; /* address offset: 0x0144 */
62 uint32_t reserved0148; /* address offset: 0x0148 */
63 uint32_t status19; /* address offset: 0x014c */
64 uint32_t reserved0150[10]; /* address offset: 0x0150 */
65 uint32_t status30; /* address offset: 0x0178 */
72 uint32_t soc_con0; /* address offset: 0x0000 */
73 uint32_t soc_con1; /* address offset: 0x0004 */
74 uint32_t soc_con2; /* address offset: 0x0008 */
75 uint32_t soc_con3; /* address offset: 0x000c */
76 uint32_t soc_con4; /* address offset: 0x0010 */
77 uint32_t soc_con5; /* address offset: 0x0014 */
78 uint32_t soc_con6; /* address offset: 0x0018 */
79 uint32_t soc_con7; /* address offset: 0x001c */
80 uint32_t soc_con8; /* address offset: 0x0020 */
81 uint32_t soc_con9; /* address offset: 0x0024 */
82 uint32_t soc_con10; /* address offset: 0x0028 */
83 uint32_t soc_con11; /* address offset: 0x002c */
84 uint32_t soc_con12; /* address offset: 0x0030 */
85 uint32_t soc_con13; /* address offset: 0x0034 */
86 uint32_t soc_con14; /* address offset: 0x0038 */
87 uint32_t soc_con15; /* address offset: 0x003c */
88 uint32_t reserved0040[16]; /* address offset: 0x0040 */
89 uint32_t aad_con0; /* address offset: 0x0080 */
90 uint32_t reserved0084[47]; /* address offset: 0x0084 */
91 uint32_t men_con0; /* address offset: 0x0140 */
92 uint32_t men_con1; /* address offset: 0x0144 */
93 uint32_t men_con2; /* address offset: 0x0148 */
94 uint32_t reserved014c; /* address offset: 0x014c */
95 uint32_t soc_special0; /* address offset: 0x0150 */
96 uint32_t reserved0154[3]; /* address offset: 0x0154 */
97 uint32_t soc_aov_int_con; /* address offset: 0x0160 */
98 uint32_t reserved0164[3]; /* address offset: 0x0164 */
99 uint32_t soc_status0; /* address offset: 0x0170 */
100 uint32_t soc_status1; /* address offset: 0x0174 */
101 uint32_t soc_status2; /* address offset: 0x0178 */
102 uint32_t reserved017c[33]; /* address offset: 0x017c */
103 uint32_t os_reg0; /* address offset: 0x0200 */
104 uint32_t os_reg1; /* address offset: 0x0204 */
105 uint32_t os_reg2; /* address offset: 0x0208 */
106 uint32_t os_reg3; /* address offset: 0x020c */
107 uint32_t os_reg4; /* address offset: 0x0210 */
108 uint32_t os_reg5; /* address offset: 0x0214 */
109 uint32_t os_reg6; /* address offset: 0x0218 */
110 uint32_t os_reg7; /* address offset: 0x021c */
111 uint32_t os_reg8; /* address offset: 0x0220 */
112 uint32_t os_reg9; /* address offset: 0x0224 */
113 uint32_t os_reg10; /* address offset: 0x0228 */
114 uint32_t os_reg11; /* address offset: 0x022c */
115 uint32_t reset_function_status; /* address offset: 0x0230 */
116 uint32_t reset_function_clr; /* address offset: 0x0234 */
117 uint32_t reserved0238[82]; /* address offset: 0x0238 */
118 uint32_t sig_detect_con; /* address offset: 0x0380 */
119 uint32_t reserved0384[3]; /* address offset: 0x0384 */
120 uint32_t sig_detect_status; /* address offset: 0x0390 */
121 uint32_t reserved0394[3]; /* address offset: 0x0394 */
122 uint32_t sig_detect_status_clear; /* address offset: 0x03a0 */
123 uint32_t reserved03a4[3]; /* address offset: 0x03a4 */
124 uint32_t sdmmc_det_counter; /* address offset: 0x03b0 */
131 uint32_t mem_grf_spra; /* address offset: 0x0000 */
132 uint32_t mem_grf_dpra; /* address offset: 0x0004 */
133 uint32_t npu_grf_cbuf_mem_soft_gate; /* address offset: 0x0008 */
134 uint32_t npu_grf_cfg_nsp_slv_addr; /* address offset: 0x000c */
135 uint32_t npu_grf_nsp_mem_soft_gate; /* address offset: 0x0010 */
136 uint32_t npu_grf_cfg_use_nsp; /* address offset: 0x0014 */
137 uint32_t npu_grf_shape; /* address offset: 0x0018 */
144 uint32_t mem_grf_spra; /* address offset: 0x0000 */
145 uint32_t mem_grf_dpra; /* address offset: 0x0004 */
146 uint32_t reserved0008; /* address offset: 0x0008 */
147 uint32_t usb3_grf_con_pending; /* address offset: 0x000c */
148 uint32_t reserved0010; /* address offset: 0x0010 */
149 uint32_t mem_gate_grf_con; /* address offset: 0x0014 */
150 uint32_t hprot_grf_con; /* address offset: 0x0018 */
151 uint32_t usbhostphy_con0; /* address offset: 0x001c */
152 uint32_t usbotgphy_con0; /* address offset: 0x0020 */
153 uint32_t usbotgphy_con1; /* address offset: 0x0024 */
154 uint32_t usbotgphy_con2; /* address offset: 0x0028 */
155 uint32_t usbotgphy_con3; /* address offset: 0x002c */
156 uint32_t host0_con0; /* address offset: 0x0030 */
157 uint32_t host0_con1; /* address offset: 0x0034 */
158 uint32_t usb3otg0_con0; /* address offset: 0x0038 */
159 uint32_t usb3otg0_con1; /* address offset: 0x003c */
160 uint32_t reserved0040[13]; /* address offset: 0x0040 */
161 uint32_t otgphy_int_en; /* address offset: 0x0074 */
162 uint32_t otgphy_int_st; /* address offset: 0x0078 */
163 uint32_t otgphy_int_st_clr; /* address offset: 0x007c */
164 uint32_t otgphy_ls_con; /* address offset: 0x0080 */
165 uint32_t otgphy_dis_con; /* address offset: 0x0084 */
166 uint32_t otgphy_bvalid_con; /* address offset: 0x0088 */
167 uint32_t otgphy_id_con; /* address offset: 0x008c */
168 uint32_t hostphy_int_en; /* address offset: 0x0090 */
169 uint32_t hostphy_int_st; /* address offset: 0x0094 */
170 uint32_t hostphy_int_st_clr; /* address offset: 0x0098 */
171 uint32_t hostphy_ls_con; /* address offset: 0x009c */
172 uint32_t hostphy_dis_con; /* address offset: 0x00a0 */
173 uint32_t hostphy_bvalid_con; /* address offset: 0x00a4 */
174 uint32_t hostphy_id_con; /* address offset: 0x00a8 */
175 uint32_t reserved00ac[21]; /* address offset: 0x00ac */
176 uint32_t usb3otg0_status; /* address offset: 0x0100 */
177 uint32_t usb3otg0_status_cb; /* address offset: 0x0104 */
178 uint32_t usb3otg0_status_lat0; /* address offset: 0x0108 */
179 uint32_t usb3otg0_status_lat1; /* address offset: 0x010c */
180 uint32_t usbphy_st; /* address offset: 0x0110 */
181 uint32_t host0_st; /* address offset: 0x0114 */
182 uint32_t usb3_host_utmi_st; /* address offset: 0x0118 */
183 uint32_t rtc_grf_st; /* address offset: 0x011c */
190 uint32_t pipe_con0; /* address offset: 0x0000 */
191 uint32_t pipe_con1; /* address offset: 0x0004 */
192 uint32_t pipe_con2; /* address offset: 0x0008 */
193 uint32_t pipe_con3; /* address offset: 0x000c */
194 uint32_t pipe_con4; /* address offset: 0x0010 */
195 uint32_t reserved0014[8]; /* address offset: 0x0014 */
196 uint32_t pipe_status1; /* address offset: 0x0034 */
197 uint32_t reserved0038[18]; /* address offset: 0x0038 */
198 uint32_t lfps_det_con; /* address offset: 0x0080 */
199 uint32_t reserved0084[7]; /* address offset: 0x0084 */
200 uint32_t phy_int_en; /* address offset: 0x00a0 */
201 uint32_t phy_int_status; /* address offset: 0x00a4 */
208 uint32_t mem_grf_spra; /* address offset: 0x0000 */
209 uint32_t mem_grf_dpra; /* address offset: 0x0004 */
210 uint32_t mem_grf_rom; /* address offset: 0x0008 */
211 uint32_t bus_grf_misc; /* address offset: 0x000c */
212 uint32_t mem_con_gate; /* address offset: 0x0010 */
213 uint32_t bus_grf_hprot_stall; /* address offset: 0x0014 */
214 uint32_t hpmcu_cache_misc; /* address offset: 0x0018 */
215 uint32_t hpmcu_cache_addr_start; /* address offset: 0x001c */
216 uint32_t hpmcu_cache_addr_end; /* address offset: 0x0020 */
217 uint32_t hpmcu_code_addr_start; /* address offset: 0x0024 */
218 uint32_t hpmcu_sram_addr_start; /* address offset: 0x0028 */
219 uint32_t hpmcu_exsram_addr_start; /* address offset: 0x002c */
220 uint32_t biu_con0; /* address offset: 0x0030 */
221 uint32_t biu_con1; /* address offset: 0x0034 */
222 uint32_t uart_grf_rts_cts; /* address offset: 0x0038 */
223 uint32_t uart_grf_dma_bypass; /* address offset: 0x003c */
224 uint32_t audio_con0; /* address offset: 0x0040 */
225 uint32_t reserved0044; /* address offset: 0x0044 */
226 uint32_t audio_con2; /* address offset: 0x0048 */
227 uint32_t otp_con; /* address offset: 0x004c */
228 uint32_t tsadc_grf_con0; /* address offset: 0x0050 */
229 uint32_t tsadc_grf_con1; /* address offset: 0x0054 */
230 uint32_t tsadc_grf_con2; /* address offset: 0x0058 */
231 uint32_t tsadc_grf_con3; /* address offset: 0x005c */
232 uint32_t tsadc_grf_con4; /* address offset: 0x0060 */
233 uint32_t tsadc_grf_con5; /* address offset: 0x0064 */
234 uint32_t tsadc_grf_con6; /* address offset: 0x0068 */
235 uint32_t reserved006c[37]; /* address offset: 0x006c */
236 uint32_t biu_status0; /* address offset: 0x0100 */
237 uint32_t biu_status1; /* address offset: 0x0104 */
238 uint32_t biu_status2; /* address offset: 0x0108 */
239 uint32_t hpmcu_cache_status; /* address offset: 0x010c */
240 uint32_t tsadc_grf_status0; /* address offset: 0x0110 */
241 uint32_t tsadc_grf_status1; /* address offset: 0x0114 */
242 uint32_t sys_status; /* address offset: 0x0118 */
243 uint32_t reserved011c[441]; /* address offset: 0x011c */
244 uint32_t chip_id; /* address offset: 0x0800 */
245 uint32_t chip_version; /* address offset: 0x0804 */
252 uint32_t mem_grf_spra; /* address offset: 0x0000 */
253 uint32_t mem_grf_dpra; /* address offset: 0x0004 */
254 uint32_t vcp_grf_aisp_mem_con; /* address offset: 0x0008 */
261 uint32_t mem_grf_spra; /* address offset: 0x0000 */
262 uint32_t mem_grf_dpra; /* address offset: 0x0004 */
263 uint32_t mem_gate_grf_con; /* address offset: 0x0008 */
264 uint32_t dsi_grf_con; /* address offset: 0x000c */
265 uint32_t dsiphy_grf_con; /* address offset: 0x0010 */
266 uint32_t rkmmu_grf_con; /* address offset: 0x0014 */
267 uint32_t reserved0018[14]; /* address offset: 0x0018 */
268 uint32_t vdo_grf_status0; /* address offset: 0x0050 */
269 uint32_t vdo_grf_status1; /* address offset: 0x0054 */
276 uint32_t mem_grf_spra; /* address offset: 0x0000 */
277 uint32_t mem_grf_dpra; /* address offset: 0x0004 */
278 uint32_t vepu_grf_con0; /* address offset: 0x0008 */
279 uint32_t saradc0_grf_con0; /* address offset: 0x000c */
280 uint32_t saradc0_grf_con1; /* address offset: 0x0010 */
281 uint32_t saradc0_grf_con2; /* address offset: 0x0014 */
282 uint32_t reserved0018[3]; /* address offset: 0x0018 */
283 uint32_t sdmmc1_det_cnt; /* address offset: 0x0024 */
284 uint32_t sdmmc1_sig_detect_con; /* address offset: 0x0028 */
285 uint32_t sdmmc1_sig_detect_status; /* address offset: 0x002c */
286 uint32_t sdmmc1_status_clr; /* address offset: 0x0030 */
293 uint32_t mem_con_spra; /* address offset: 0x0000 */
294 uint32_t mem_con_dpra; /* address offset: 0x0004 */
295 uint32_t vi_grf_status; /* address offset: 0x0008 */
296 uint32_t reserved000c; /* address offset: 0x000c */
297 uint32_t csiphy0_grf_con; /* address offset: 0x0010 */
298 uint32_t csiphy1_grf_con; /* address offset: 0x0014 */
299 uint32_t csiphy0_grf_status; /* address offset: 0x0018 */
300 uint32_t csiphy1_grf_status; /* address offset: 0x001c */
301 uint32_t misc_grf_con; /* address offset: 0x0020 */
302 uint32_t reserved0024[11]; /* address offset: 0x0024 */
303 uint32_t gmac_grf_con0; /* address offset: 0x0050 */
304 uint32_t gmac_dma_ack; /* address offset: 0x0054 */
305 uint32_t reserved0058[2]; /* address offset: 0x0058 */
306 uint32_t gmac_grf_status0; /* address offset: 0x0060 */
307 uint32_t gmac_grf_status1; /* address offset: 0x0064 */
308 uint32_t gmac_grf_status2; /* address offset: 0x0068 */
309 uint32_t reserved006c[5]; /* address offset: 0x006c */
310 uint32_t saradc1_grf_con0; /* address offset: 0x0080 */
311 uint32_t saradc1_grf_con1; /* address offset: 0x0084 */
312 uint32_t saradc1_grf_con2; /* address offset: 0x0088 */
313 uint32_t reserved008c; /* address offset: 0x008c */
314 uint32_t saradc2_grf_con0; /* address offset: 0x0090 */
315 uint32_t saradc2_grf_con1; /* address offset: 0x0094 */
316 uint32_t saradc2_grf_con2; /* address offset: 0x0098 */
317 uint32_t reserved009c[6]; /* address offset: 0x009c */
318 uint32_t rkmacphy_grf_con0; /* address offset: 0x00b4 */
319 uint32_t rkmacphy_grf_con1; /* address offset: 0x00b8 */
320 uint32_t rkmacphy_grf_con2; /* address offset: 0x00bc */
321 uint32_t rkmacphy_grf_status; /* address offset: 0x00c0 */
322 uint32_t rkmacphy_calib_con; /* address offset: 0x00c4 */