1*4e72b326SXuhui Lin /* 2*4e72b326SXuhui Lin * (C) Copyright 2025 Rockchip Electronics Co., Ltd. 3*4e72b326SXuhui Lin * 4*4e72b326SXuhui Lin * SPDX-License-Identifier: GPL-2.0+ 5*4e72b326SXuhui Lin */ 6*4e72b326SXuhui Lin #ifndef _ASM_ARCH_GRF_RV1126B_H 7*4e72b326SXuhui Lin #define _ASM_ARCH_GRF_RV1126B_H 8*4e72b326SXuhui Lin 9*4e72b326SXuhui Lin #include <common.h> 10*4e72b326SXuhui Lin 11*4e72b326SXuhui Lin /* cpu_grf register structure define */ 12*4e72b326SXuhui Lin struct rv1126b_cpu_grf_reg { 13*4e72b326SXuhui Lin uint32_t con0; /* address offset: 0x0000 */ 14*4e72b326SXuhui Lin uint32_t con1; /* address offset: 0x0004 */ 15*4e72b326SXuhui Lin uint32_t mem_cfg_uhdspra; /* address offset: 0x0008 */ 16*4e72b326SXuhui Lin uint32_t status0; /* address offset: 0x000c */ 17*4e72b326SXuhui Lin uint32_t status1; /* address offset: 0x0010 */ 18*4e72b326SXuhui Lin }; 19*4e72b326SXuhui Lin 20*4e72b326SXuhui Lin check_member(rv1126b_cpu_grf_reg, status1, 0x0010); 21*4e72b326SXuhui Lin 22*4e72b326SXuhui Lin /* ddr_grf register structure define */ 23*4e72b326SXuhui Lin struct rv1126b_ddr_grf_reg { 24*4e72b326SXuhui Lin uint32_t con0; /* address offset: 0x0000 */ 25*4e72b326SXuhui Lin uint32_t con1; /* address offset: 0x0004 */ 26*4e72b326SXuhui Lin uint32_t reserved0008[2]; /* address offset: 0x0008 */ 27*4e72b326SXuhui Lin uint32_t con4; /* address offset: 0x0010 */ 28*4e72b326SXuhui Lin uint32_t reserved0014[7]; /* address offset: 0x0014 */ 29*4e72b326SXuhui Lin uint32_t con12; /* address offset: 0x0030 */ 30*4e72b326SXuhui Lin uint32_t con13; /* address offset: 0x0034 */ 31*4e72b326SXuhui Lin uint32_t con14; /* address offset: 0x0038 */ 32*4e72b326SXuhui Lin uint32_t con15; /* address offset: 0x003c */ 33*4e72b326SXuhui Lin uint32_t con16; /* address offset: 0x0040 */ 34*4e72b326SXuhui Lin uint32_t con17; /* address offset: 0x0044 */ 35*4e72b326SXuhui Lin uint32_t con18; /* address offset: 0x0048 */ 36*4e72b326SXuhui Lin uint32_t reserved004c; /* address offset: 0x004c */ 37*4e72b326SXuhui Lin uint32_t con20; /* address offset: 0x0050 */ 38*4e72b326SXuhui Lin uint32_t con21; /* address offset: 0x0054 */ 39*4e72b326SXuhui Lin uint32_t con22; /* address offset: 0x0058 */ 40*4e72b326SXuhui Lin uint32_t con23; /* address offset: 0x005c */ 41*4e72b326SXuhui Lin uint32_t reserved0060[8]; /* address offset: 0x0060 */ 42*4e72b326SXuhui Lin uint32_t probe_ctrl; /* address offset: 0x0080 */ 43*4e72b326SXuhui Lin uint32_t reserved0084[31]; /* address offset: 0x0084 */ 44*4e72b326SXuhui Lin uint32_t status0; /* address offset: 0x0100 */ 45*4e72b326SXuhui Lin uint32_t status1; /* address offset: 0x0104 */ 46*4e72b326SXuhui Lin uint32_t status2; /* address offset: 0x0108 */ 47*4e72b326SXuhui Lin uint32_t status3; /* address offset: 0x010c */ 48*4e72b326SXuhui Lin uint32_t status4; /* address offset: 0x0110 */ 49*4e72b326SXuhui Lin uint32_t status5; /* address offset: 0x0114 */ 50*4e72b326SXuhui Lin uint32_t status6; /* address offset: 0x0118 */ 51*4e72b326SXuhui Lin uint32_t status7; /* address offset: 0x011c */ 52*4e72b326SXuhui Lin uint32_t status8; /* address offset: 0x0120 */ 53*4e72b326SXuhui Lin uint32_t status9; /* address offset: 0x0124 */ 54*4e72b326SXuhui Lin uint32_t status10; /* address offset: 0x0128 */ 55*4e72b326SXuhui Lin uint32_t status11; /* address offset: 0x012c */ 56*4e72b326SXuhui Lin uint32_t status12; /* address offset: 0x0130 */ 57*4e72b326SXuhui Lin uint32_t status13; /* address offset: 0x0134 */ 58*4e72b326SXuhui Lin uint32_t status14; /* address offset: 0x0138 */ 59*4e72b326SXuhui Lin uint32_t status15; /* address offset: 0x013c */ 60*4e72b326SXuhui Lin uint32_t status16; /* address offset: 0x0140 */ 61*4e72b326SXuhui Lin uint32_t status17; /* address offset: 0x0144 */ 62*4e72b326SXuhui Lin uint32_t reserved0148; /* address offset: 0x0148 */ 63*4e72b326SXuhui Lin uint32_t status19; /* address offset: 0x014c */ 64*4e72b326SXuhui Lin uint32_t reserved0150[10]; /* address offset: 0x0150 */ 65*4e72b326SXuhui Lin uint32_t status30; /* address offset: 0x0178 */ 66*4e72b326SXuhui Lin }; 67*4e72b326SXuhui Lin 68*4e72b326SXuhui Lin check_member(rv1126b_ddr_grf_reg, status30, 0x0178); 69*4e72b326SXuhui Lin 70*4e72b326SXuhui Lin /* pmu_grf register structure define */ 71*4e72b326SXuhui Lin struct rv1126b_pmu_grf_reg { 72*4e72b326SXuhui Lin uint32_t soc_con0; /* address offset: 0x0000 */ 73*4e72b326SXuhui Lin uint32_t soc_con1; /* address offset: 0x0004 */ 74*4e72b326SXuhui Lin uint32_t soc_con2; /* address offset: 0x0008 */ 75*4e72b326SXuhui Lin uint32_t soc_con3; /* address offset: 0x000c */ 76*4e72b326SXuhui Lin uint32_t soc_con4; /* address offset: 0x0010 */ 77*4e72b326SXuhui Lin uint32_t soc_con5; /* address offset: 0x0014 */ 78*4e72b326SXuhui Lin uint32_t soc_con6; /* address offset: 0x0018 */ 79*4e72b326SXuhui Lin uint32_t soc_con7; /* address offset: 0x001c */ 80*4e72b326SXuhui Lin uint32_t soc_con8; /* address offset: 0x0020 */ 81*4e72b326SXuhui Lin uint32_t soc_con9; /* address offset: 0x0024 */ 82*4e72b326SXuhui Lin uint32_t soc_con10; /* address offset: 0x0028 */ 83*4e72b326SXuhui Lin uint32_t soc_con11; /* address offset: 0x002c */ 84*4e72b326SXuhui Lin uint32_t soc_con12; /* address offset: 0x0030 */ 85*4e72b326SXuhui Lin uint32_t soc_con13; /* address offset: 0x0034 */ 86*4e72b326SXuhui Lin uint32_t soc_con14; /* address offset: 0x0038 */ 87*4e72b326SXuhui Lin uint32_t soc_con15; /* address offset: 0x003c */ 88*4e72b326SXuhui Lin uint32_t reserved0040[16]; /* address offset: 0x0040 */ 89*4e72b326SXuhui Lin uint32_t aad_con0; /* address offset: 0x0080 */ 90*4e72b326SXuhui Lin uint32_t reserved0084[47]; /* address offset: 0x0084 */ 91*4e72b326SXuhui Lin uint32_t men_con0; /* address offset: 0x0140 */ 92*4e72b326SXuhui Lin uint32_t men_con1; /* address offset: 0x0144 */ 93*4e72b326SXuhui Lin uint32_t men_con2; /* address offset: 0x0148 */ 94*4e72b326SXuhui Lin uint32_t reserved014c; /* address offset: 0x014c */ 95*4e72b326SXuhui Lin uint32_t soc_special0; /* address offset: 0x0150 */ 96*4e72b326SXuhui Lin uint32_t reserved0154[3]; /* address offset: 0x0154 */ 97*4e72b326SXuhui Lin uint32_t soc_aov_int_con; /* address offset: 0x0160 */ 98*4e72b326SXuhui Lin uint32_t reserved0164[3]; /* address offset: 0x0164 */ 99*4e72b326SXuhui Lin uint32_t soc_status0; /* address offset: 0x0170 */ 100*4e72b326SXuhui Lin uint32_t soc_status1; /* address offset: 0x0174 */ 101*4e72b326SXuhui Lin uint32_t soc_status2; /* address offset: 0x0178 */ 102*4e72b326SXuhui Lin uint32_t reserved017c[33]; /* address offset: 0x017c */ 103*4e72b326SXuhui Lin uint32_t os_reg0; /* address offset: 0x0200 */ 104*4e72b326SXuhui Lin uint32_t os_reg1; /* address offset: 0x0204 */ 105*4e72b326SXuhui Lin uint32_t os_reg2; /* address offset: 0x0208 */ 106*4e72b326SXuhui Lin uint32_t os_reg3; /* address offset: 0x020c */ 107*4e72b326SXuhui Lin uint32_t os_reg4; /* address offset: 0x0210 */ 108*4e72b326SXuhui Lin uint32_t os_reg5; /* address offset: 0x0214 */ 109*4e72b326SXuhui Lin uint32_t os_reg6; /* address offset: 0x0218 */ 110*4e72b326SXuhui Lin uint32_t os_reg7; /* address offset: 0x021c */ 111*4e72b326SXuhui Lin uint32_t os_reg8; /* address offset: 0x0220 */ 112*4e72b326SXuhui Lin uint32_t os_reg9; /* address offset: 0x0224 */ 113*4e72b326SXuhui Lin uint32_t os_reg10; /* address offset: 0x0228 */ 114*4e72b326SXuhui Lin uint32_t os_reg11; /* address offset: 0x022c */ 115*4e72b326SXuhui Lin uint32_t reset_function_status; /* address offset: 0x0230 */ 116*4e72b326SXuhui Lin uint32_t reset_function_clr; /* address offset: 0x0234 */ 117*4e72b326SXuhui Lin uint32_t reserved0238[82]; /* address offset: 0x0238 */ 118*4e72b326SXuhui Lin uint32_t sig_detect_con; /* address offset: 0x0380 */ 119*4e72b326SXuhui Lin uint32_t reserved0384[3]; /* address offset: 0x0384 */ 120*4e72b326SXuhui Lin uint32_t sig_detect_status; /* address offset: 0x0390 */ 121*4e72b326SXuhui Lin uint32_t reserved0394[3]; /* address offset: 0x0394 */ 122*4e72b326SXuhui Lin uint32_t sig_detect_status_clear; /* address offset: 0x03a0 */ 123*4e72b326SXuhui Lin uint32_t reserved03a4[3]; /* address offset: 0x03a4 */ 124*4e72b326SXuhui Lin uint32_t sdmmc_det_counter; /* address offset: 0x03b0 */ 125*4e72b326SXuhui Lin }; 126*4e72b326SXuhui Lin 127*4e72b326SXuhui Lin check_member(rv1126b_pmu_grf_reg, sdmmc_det_counter, 0x03b0); 128*4e72b326SXuhui Lin 129*4e72b326SXuhui Lin /* npu_grf register structure define */ 130*4e72b326SXuhui Lin struct rv1126b_npu_grf_reg { 131*4e72b326SXuhui Lin uint32_t mem_grf_spra; /* address offset: 0x0000 */ 132*4e72b326SXuhui Lin uint32_t mem_grf_dpra; /* address offset: 0x0004 */ 133*4e72b326SXuhui Lin uint32_t npu_grf_cbuf_mem_soft_gate; /* address offset: 0x0008 */ 134*4e72b326SXuhui Lin uint32_t npu_grf_cfg_nsp_slv_addr; /* address offset: 0x000c */ 135*4e72b326SXuhui Lin uint32_t npu_grf_nsp_mem_soft_gate; /* address offset: 0x0010 */ 136*4e72b326SXuhui Lin uint32_t npu_grf_cfg_use_nsp; /* address offset: 0x0014 */ 137*4e72b326SXuhui Lin uint32_t npu_grf_shape; /* address offset: 0x0018 */ 138*4e72b326SXuhui Lin }; 139*4e72b326SXuhui Lin 140*4e72b326SXuhui Lin check_member(rv1126b_npu_grf_reg, npu_grf_shape, 0x0018); 141*4e72b326SXuhui Lin 142*4e72b326SXuhui Lin /* peri_grf register structure define */ 143*4e72b326SXuhui Lin struct rv1126b_peri_grf_reg { 144*4e72b326SXuhui Lin uint32_t mem_grf_spra; /* address offset: 0x0000 */ 145*4e72b326SXuhui Lin uint32_t mem_grf_dpra; /* address offset: 0x0004 */ 146*4e72b326SXuhui Lin uint32_t reserved0008; /* address offset: 0x0008 */ 147*4e72b326SXuhui Lin uint32_t usb3_grf_con_pending; /* address offset: 0x000c */ 148*4e72b326SXuhui Lin uint32_t reserved0010; /* address offset: 0x0010 */ 149*4e72b326SXuhui Lin uint32_t mem_gate_grf_con; /* address offset: 0x0014 */ 150*4e72b326SXuhui Lin uint32_t hprot_grf_con; /* address offset: 0x0018 */ 151*4e72b326SXuhui Lin uint32_t usbhostphy_con0; /* address offset: 0x001c */ 152*4e72b326SXuhui Lin uint32_t usbotgphy_con0; /* address offset: 0x0020 */ 153*4e72b326SXuhui Lin uint32_t usbotgphy_con1; /* address offset: 0x0024 */ 154*4e72b326SXuhui Lin uint32_t usbotgphy_con2; /* address offset: 0x0028 */ 155*4e72b326SXuhui Lin uint32_t usbotgphy_con3; /* address offset: 0x002c */ 156*4e72b326SXuhui Lin uint32_t host0_con0; /* address offset: 0x0030 */ 157*4e72b326SXuhui Lin uint32_t host0_con1; /* address offset: 0x0034 */ 158*4e72b326SXuhui Lin uint32_t usb3otg0_con0; /* address offset: 0x0038 */ 159*4e72b326SXuhui Lin uint32_t usb3otg0_con1; /* address offset: 0x003c */ 160*4e72b326SXuhui Lin uint32_t reserved0040[13]; /* address offset: 0x0040 */ 161*4e72b326SXuhui Lin uint32_t otgphy_int_en; /* address offset: 0x0074 */ 162*4e72b326SXuhui Lin uint32_t otgphy_int_st; /* address offset: 0x0078 */ 163*4e72b326SXuhui Lin uint32_t otgphy_int_st_clr; /* address offset: 0x007c */ 164*4e72b326SXuhui Lin uint32_t otgphy_ls_con; /* address offset: 0x0080 */ 165*4e72b326SXuhui Lin uint32_t otgphy_dis_con; /* address offset: 0x0084 */ 166*4e72b326SXuhui Lin uint32_t otgphy_bvalid_con; /* address offset: 0x0088 */ 167*4e72b326SXuhui Lin uint32_t otgphy_id_con; /* address offset: 0x008c */ 168*4e72b326SXuhui Lin uint32_t hostphy_int_en; /* address offset: 0x0090 */ 169*4e72b326SXuhui Lin uint32_t hostphy_int_st; /* address offset: 0x0094 */ 170*4e72b326SXuhui Lin uint32_t hostphy_int_st_clr; /* address offset: 0x0098 */ 171*4e72b326SXuhui Lin uint32_t hostphy_ls_con; /* address offset: 0x009c */ 172*4e72b326SXuhui Lin uint32_t hostphy_dis_con; /* address offset: 0x00a0 */ 173*4e72b326SXuhui Lin uint32_t hostphy_bvalid_con; /* address offset: 0x00a4 */ 174*4e72b326SXuhui Lin uint32_t hostphy_id_con; /* address offset: 0x00a8 */ 175*4e72b326SXuhui Lin uint32_t reserved00ac[21]; /* address offset: 0x00ac */ 176*4e72b326SXuhui Lin uint32_t usb3otg0_status; /* address offset: 0x0100 */ 177*4e72b326SXuhui Lin uint32_t usb3otg0_status_cb; /* address offset: 0x0104 */ 178*4e72b326SXuhui Lin uint32_t usb3otg0_status_lat0; /* address offset: 0x0108 */ 179*4e72b326SXuhui Lin uint32_t usb3otg0_status_lat1; /* address offset: 0x010c */ 180*4e72b326SXuhui Lin uint32_t usbphy_st; /* address offset: 0x0110 */ 181*4e72b326SXuhui Lin uint32_t host0_st; /* address offset: 0x0114 */ 182*4e72b326SXuhui Lin uint32_t usb3_host_utmi_st; /* address offset: 0x0118 */ 183*4e72b326SXuhui Lin uint32_t rtc_grf_st; /* address offset: 0x011c */ 184*4e72b326SXuhui Lin }; 185*4e72b326SXuhui Lin 186*4e72b326SXuhui Lin check_member(rv1126b_peri_grf_reg, rtc_grf_st, 0x011c); 187*4e72b326SXuhui Lin 188*4e72b326SXuhui Lin /* usb3_phy_grf register structure define */ 189*4e72b326SXuhui Lin struct rv1126b_usb3_phy_grf_reg { 190*4e72b326SXuhui Lin uint32_t pipe_con0; /* address offset: 0x0000 */ 191*4e72b326SXuhui Lin uint32_t pipe_con1; /* address offset: 0x0004 */ 192*4e72b326SXuhui Lin uint32_t pipe_con2; /* address offset: 0x0008 */ 193*4e72b326SXuhui Lin uint32_t pipe_con3; /* address offset: 0x000c */ 194*4e72b326SXuhui Lin uint32_t pipe_con4; /* address offset: 0x0010 */ 195*4e72b326SXuhui Lin uint32_t reserved0014[8]; /* address offset: 0x0014 */ 196*4e72b326SXuhui Lin uint32_t pipe_status1; /* address offset: 0x0034 */ 197*4e72b326SXuhui Lin uint32_t reserved0038[18]; /* address offset: 0x0038 */ 198*4e72b326SXuhui Lin uint32_t lfps_det_con; /* address offset: 0x0080 */ 199*4e72b326SXuhui Lin uint32_t reserved0084[7]; /* address offset: 0x0084 */ 200*4e72b326SXuhui Lin uint32_t phy_int_en; /* address offset: 0x00a0 */ 201*4e72b326SXuhui Lin uint32_t phy_int_status; /* address offset: 0x00a4 */ 202*4e72b326SXuhui Lin }; 203*4e72b326SXuhui Lin 204*4e72b326SXuhui Lin check_member(rv1126b_usb3_phy_grf_reg, phy_int_status, 0x00a4); 205*4e72b326SXuhui Lin 206*4e72b326SXuhui Lin /* sys_grf register structure define */ 207*4e72b326SXuhui Lin struct rv1126b_sys_grf_reg { 208*4e72b326SXuhui Lin uint32_t mem_grf_spra; /* address offset: 0x0000 */ 209*4e72b326SXuhui Lin uint32_t mem_grf_dpra; /* address offset: 0x0004 */ 210*4e72b326SXuhui Lin uint32_t mem_grf_rom; /* address offset: 0x0008 */ 211*4e72b326SXuhui Lin uint32_t bus_grf_misc; /* address offset: 0x000c */ 212*4e72b326SXuhui Lin uint32_t mem_con_gate; /* address offset: 0x0010 */ 213*4e72b326SXuhui Lin uint32_t bus_grf_hprot_stall; /* address offset: 0x0014 */ 214*4e72b326SXuhui Lin uint32_t hpmcu_cache_misc; /* address offset: 0x0018 */ 215*4e72b326SXuhui Lin uint32_t hpmcu_cache_addr_start; /* address offset: 0x001c */ 216*4e72b326SXuhui Lin uint32_t hpmcu_cache_addr_end; /* address offset: 0x0020 */ 217*4e72b326SXuhui Lin uint32_t hpmcu_code_addr_start; /* address offset: 0x0024 */ 218*4e72b326SXuhui Lin uint32_t hpmcu_sram_addr_start; /* address offset: 0x0028 */ 219*4e72b326SXuhui Lin uint32_t hpmcu_exsram_addr_start; /* address offset: 0x002c */ 220*4e72b326SXuhui Lin uint32_t biu_con0; /* address offset: 0x0030 */ 221*4e72b326SXuhui Lin uint32_t biu_con1; /* address offset: 0x0034 */ 222*4e72b326SXuhui Lin uint32_t uart_grf_rts_cts; /* address offset: 0x0038 */ 223*4e72b326SXuhui Lin uint32_t uart_grf_dma_bypass; /* address offset: 0x003c */ 224*4e72b326SXuhui Lin uint32_t audio_con0; /* address offset: 0x0040 */ 225*4e72b326SXuhui Lin uint32_t reserved0044; /* address offset: 0x0044 */ 226*4e72b326SXuhui Lin uint32_t audio_con2; /* address offset: 0x0048 */ 227*4e72b326SXuhui Lin uint32_t otp_con; /* address offset: 0x004c */ 228*4e72b326SXuhui Lin uint32_t tsadc_grf_con0; /* address offset: 0x0050 */ 229*4e72b326SXuhui Lin uint32_t tsadc_grf_con1; /* address offset: 0x0054 */ 230*4e72b326SXuhui Lin uint32_t tsadc_grf_con2; /* address offset: 0x0058 */ 231*4e72b326SXuhui Lin uint32_t tsadc_grf_con3; /* address offset: 0x005c */ 232*4e72b326SXuhui Lin uint32_t tsadc_grf_con4; /* address offset: 0x0060 */ 233*4e72b326SXuhui Lin uint32_t tsadc_grf_con5; /* address offset: 0x0064 */ 234*4e72b326SXuhui Lin uint32_t tsadc_grf_con6; /* address offset: 0x0068 */ 235*4e72b326SXuhui Lin uint32_t reserved006c[37]; /* address offset: 0x006c */ 236*4e72b326SXuhui Lin uint32_t biu_status0; /* address offset: 0x0100 */ 237*4e72b326SXuhui Lin uint32_t biu_status1; /* address offset: 0x0104 */ 238*4e72b326SXuhui Lin uint32_t biu_status2; /* address offset: 0x0108 */ 239*4e72b326SXuhui Lin uint32_t hpmcu_cache_status; /* address offset: 0x010c */ 240*4e72b326SXuhui Lin uint32_t tsadc_grf_status0; /* address offset: 0x0110 */ 241*4e72b326SXuhui Lin uint32_t tsadc_grf_status1; /* address offset: 0x0114 */ 242*4e72b326SXuhui Lin uint32_t sys_status; /* address offset: 0x0118 */ 243*4e72b326SXuhui Lin uint32_t reserved011c[441]; /* address offset: 0x011c */ 244*4e72b326SXuhui Lin uint32_t chip_id; /* address offset: 0x0800 */ 245*4e72b326SXuhui Lin uint32_t chip_version; /* address offset: 0x0804 */ 246*4e72b326SXuhui Lin }; 247*4e72b326SXuhui Lin 248*4e72b326SXuhui Lin check_member(rv1126b_sys_grf_reg, chip_version, 0x0804); 249*4e72b326SXuhui Lin 250*4e72b326SXuhui Lin /* vcp_grf register structure define */ 251*4e72b326SXuhui Lin struct rv1126b_vcp_grf_reg { 252*4e72b326SXuhui Lin uint32_t mem_grf_spra; /* address offset: 0x0000 */ 253*4e72b326SXuhui Lin uint32_t mem_grf_dpra; /* address offset: 0x0004 */ 254*4e72b326SXuhui Lin uint32_t vcp_grf_aisp_mem_con; /* address offset: 0x0008 */ 255*4e72b326SXuhui Lin }; 256*4e72b326SXuhui Lin 257*4e72b326SXuhui Lin check_member(rv1126b_vcp_grf_reg, vcp_grf_aisp_mem_con, 0x0008); 258*4e72b326SXuhui Lin 259*4e72b326SXuhui Lin /* vdo_grf register structure define */ 260*4e72b326SXuhui Lin struct rv1126b_vdo_grf_reg { 261*4e72b326SXuhui Lin uint32_t mem_grf_spra; /* address offset: 0x0000 */ 262*4e72b326SXuhui Lin uint32_t mem_grf_dpra; /* address offset: 0x0004 */ 263*4e72b326SXuhui Lin uint32_t mem_gate_grf_con; /* address offset: 0x0008 */ 264*4e72b326SXuhui Lin uint32_t dsi_grf_con; /* address offset: 0x000c */ 265*4e72b326SXuhui Lin uint32_t dsiphy_grf_con; /* address offset: 0x0010 */ 266*4e72b326SXuhui Lin uint32_t rkmmu_grf_con; /* address offset: 0x0014 */ 267*4e72b326SXuhui Lin uint32_t reserved0018[14]; /* address offset: 0x0018 */ 268*4e72b326SXuhui Lin uint32_t vdo_grf_status0; /* address offset: 0x0050 */ 269*4e72b326SXuhui Lin uint32_t vdo_grf_status1; /* address offset: 0x0054 */ 270*4e72b326SXuhui Lin }; 271*4e72b326SXuhui Lin 272*4e72b326SXuhui Lin check_member(rv1126b_vdo_grf_reg, vdo_grf_status1, 0x0054); 273*4e72b326SXuhui Lin 274*4e72b326SXuhui Lin /* vepu_grf register structure define */ 275*4e72b326SXuhui Lin struct rv1126b_vepu_grf_reg { 276*4e72b326SXuhui Lin uint32_t mem_grf_spra; /* address offset: 0x0000 */ 277*4e72b326SXuhui Lin uint32_t mem_grf_dpra; /* address offset: 0x0004 */ 278*4e72b326SXuhui Lin uint32_t vepu_grf_con0; /* address offset: 0x0008 */ 279*4e72b326SXuhui Lin uint32_t saradc0_grf_con0; /* address offset: 0x000c */ 280*4e72b326SXuhui Lin uint32_t saradc0_grf_con1; /* address offset: 0x0010 */ 281*4e72b326SXuhui Lin uint32_t saradc0_grf_con2; /* address offset: 0x0014 */ 282*4e72b326SXuhui Lin uint32_t reserved0018[3]; /* address offset: 0x0018 */ 283*4e72b326SXuhui Lin uint32_t sdmmc1_det_cnt; /* address offset: 0x0024 */ 284*4e72b326SXuhui Lin uint32_t sdmmc1_sig_detect_con; /* address offset: 0x0028 */ 285*4e72b326SXuhui Lin uint32_t sdmmc1_sig_detect_status; /* address offset: 0x002c */ 286*4e72b326SXuhui Lin uint32_t sdmmc1_status_clr; /* address offset: 0x0030 */ 287*4e72b326SXuhui Lin }; 288*4e72b326SXuhui Lin 289*4e72b326SXuhui Lin check_member(rv1126b_vepu_grf_reg, sdmmc1_status_clr, 0x0030); 290*4e72b326SXuhui Lin 291*4e72b326SXuhui Lin /* vi_grf register structure define */ 292*4e72b326SXuhui Lin struct rv1126b_vi_grf_reg { 293*4e72b326SXuhui Lin uint32_t mem_con_spra; /* address offset: 0x0000 */ 294*4e72b326SXuhui Lin uint32_t mem_con_dpra; /* address offset: 0x0004 */ 295*4e72b326SXuhui Lin uint32_t vi_grf_status; /* address offset: 0x0008 */ 296*4e72b326SXuhui Lin uint32_t reserved000c; /* address offset: 0x000c */ 297*4e72b326SXuhui Lin uint32_t csiphy0_grf_con; /* address offset: 0x0010 */ 298*4e72b326SXuhui Lin uint32_t csiphy1_grf_con; /* address offset: 0x0014 */ 299*4e72b326SXuhui Lin uint32_t csiphy0_grf_status; /* address offset: 0x0018 */ 300*4e72b326SXuhui Lin uint32_t csiphy1_grf_status; /* address offset: 0x001c */ 301*4e72b326SXuhui Lin uint32_t misc_grf_con; /* address offset: 0x0020 */ 302*4e72b326SXuhui Lin uint32_t reserved0024[11]; /* address offset: 0x0024 */ 303*4e72b326SXuhui Lin uint32_t gmac_grf_con0; /* address offset: 0x0050 */ 304*4e72b326SXuhui Lin uint32_t gmac_dma_ack; /* address offset: 0x0054 */ 305*4e72b326SXuhui Lin uint32_t reserved0058[2]; /* address offset: 0x0058 */ 306*4e72b326SXuhui Lin uint32_t gmac_grf_status0; /* address offset: 0x0060 */ 307*4e72b326SXuhui Lin uint32_t gmac_grf_status1; /* address offset: 0x0064 */ 308*4e72b326SXuhui Lin uint32_t gmac_grf_status2; /* address offset: 0x0068 */ 309*4e72b326SXuhui Lin uint32_t reserved006c[5]; /* address offset: 0x006c */ 310*4e72b326SXuhui Lin uint32_t saradc1_grf_con0; /* address offset: 0x0080 */ 311*4e72b326SXuhui Lin uint32_t saradc1_grf_con1; /* address offset: 0x0084 */ 312*4e72b326SXuhui Lin uint32_t saradc1_grf_con2; /* address offset: 0x0088 */ 313*4e72b326SXuhui Lin uint32_t reserved008c; /* address offset: 0x008c */ 314*4e72b326SXuhui Lin uint32_t saradc2_grf_con0; /* address offset: 0x0090 */ 315*4e72b326SXuhui Lin uint32_t saradc2_grf_con1; /* address offset: 0x0094 */ 316*4e72b326SXuhui Lin uint32_t saradc2_grf_con2; /* address offset: 0x0098 */ 317*4e72b326SXuhui Lin uint32_t reserved009c[6]; /* address offset: 0x009c */ 318*4e72b326SXuhui Lin uint32_t rkmacphy_grf_con0; /* address offset: 0x00b4 */ 319*4e72b326SXuhui Lin uint32_t rkmacphy_grf_con1; /* address offset: 0x00b8 */ 320*4e72b326SXuhui Lin uint32_t rkmacphy_grf_con2; /* address offset: 0x00bc */ 321*4e72b326SXuhui Lin uint32_t rkmacphy_grf_status; /* address offset: 0x00c0 */ 322*4e72b326SXuhui Lin uint32_t rkmacphy_calib_con; /* address offset: 0x00c4 */ 323*4e72b326SXuhui Lin }; 324*4e72b326SXuhui Lin 325*4e72b326SXuhui Lin check_member(rv1126b_vi_grf_reg, rkmacphy_calib_con, 0x00c4); 326*4e72b326SXuhui Lin 327*4e72b326SXuhui Lin #endif /* _ASM_ARCH_GRF_RV1126B_H */ 328