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Searched refs:sel (Results 1 – 25 of 54) sorted by relevance

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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3506.c130 u32 sel; in soc_clk_dump() local
141 sel = (readl(&priv->cru->clksel_con[15]) & in soc_clk_dump()
144 if (sel == CLK_CORE_PVTPLL_SRC) in soc_clk_dump()
188 u32 sel, con, div; in rk3506_armclk_get_rate() local
192 sel = (con & CLK_CORE_SRC_SEL_MASK) >> CLK_CORE_SRC_SEL_SHIFT; in rk3506_armclk_get_rate()
195 if (sel == CLK_CORE_SEL_GPLL) in rk3506_armclk_get_rate()
197 else if (sel == CLK_CORE_SEL_V0PLL) in rk3506_armclk_get_rate()
199 else if (sel == CLK_CORE_SEL_V1PLL) in rk3506_armclk_get_rate()
212 u32 con, sel, div, old_div; in rk3506_armclk_set_rate() local
232 sel = CLK_CORE_SEL_V0PLL; in rk3506_armclk_set_rate()
[all …]
H A Dclk_rk3562.c205 u32 sel, con, div; in rk3562_bus_get_rate() local
211 sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT; in rk3562_bus_get_rate()
216 sel = (con & HCLK_BUS_SEL_MASK) >> HCLK_BUS_SEL_SHIFT; in rk3562_bus_get_rate()
221 sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT; in rk3562_bus_get_rate()
228 if (sel == ACLK_BUS_SEL_CPLL) in rk3562_bus_get_rate()
240 u32 sel, div; in rk3562_bus_set_rate() local
243 sel = ACLK_BUS_SEL_CPLL; in rk3562_bus_set_rate()
246 sel= ACLK_BUS_SEL_GPLL; in rk3562_bus_set_rate()
254 (sel << ACLK_BUS_SEL_SHIFT) | in rk3562_bus_set_rate()
260 (sel << HCLK_BUS_SEL_SHIFT) | in rk3562_bus_set_rate()
[all …]
H A Dclk_rv1106.c79 u32 con, sel, rate; in rv1106_peri_get_clk() local
84 sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT; in rv1106_peri_get_clk()
85 if (sel == ACLK_PERI_SEL_400M) in rv1106_peri_get_clk()
87 else if (sel == ACLK_PERI_SEL_200M) in rv1106_peri_get_clk()
89 else if (sel == ACLK_PERI_SEL_100M) in rv1106_peri_get_clk()
96 sel = (con & HCLK_PERI_SEL_MASK) >> HCLK_PERI_SEL_SHIFT; in rv1106_peri_get_clk()
97 if (sel == HCLK_PERI_SEL_200M) in rv1106_peri_get_clk()
99 else if (sel == HCLK_PERI_SEL_100M) in rv1106_peri_get_clk()
101 else if (sel == HCLK_PERI_SEL_50M) in rv1106_peri_get_clk()
108 sel = (con & PCLK_PERI_SEL_MASK) >> PCLK_PERI_SEL_SHIFT; in rv1106_peri_get_clk()
[all …]
H A Dclk_rk3576.c172 u32 con, sel, div, rate; in rk3576_bus_get_clk() local
177 sel = (con & ACLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
181 if (sel == ACLK_BUS_ROOT_SEL_CPLL) in rk3576_bus_get_clk()
188 sel = (con & HCLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
190 if (sel == HCLK_BUS_ROOT_SEL_200M) in rk3576_bus_get_clk()
192 else if (sel == HCLK_BUS_ROOT_SEL_100M) in rk3576_bus_get_clk()
194 else if (sel == HCLK_BUS_ROOT_SEL_50M) in rk3576_bus_get_clk()
201 sel = (con & PCLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
203 if (sel == PCLK_BUS_ROOT_SEL_100M) in rk3576_bus_get_clk()
205 else if (sel == PCLK_BUS_ROOT_SEL_50M) in rk3576_bus_get_clk()
[all …]
H A Dclk_rv1103b.c65 u32 con, sel, div, rate, prate; in rv1103b_peri_get_clk() local
70 sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT; in rv1103b_peri_get_clk()
71 if (sel == ACLK_PERI_SEL_600M) in rv1103b_peri_get_clk()
73 else if (sel == ACLK_PERI_SEL_480M) in rv1103b_peri_get_clk()
80 sel = (con & LSCLK_PERI_SEL_MASK) >> LSCLK_PERI_SEL_SHIFT; in rv1103b_peri_get_clk()
81 if (sel == LSCLK_PERI_SEL_300M) in rv1103b_peri_get_clk()
98 sel = (con & LSCLK_PMU_SEL_MASK) >> LSCLK_PMU_SEL_SHIFT; in rv1103b_peri_get_clk()
100 if (sel == LSCLK_PMU_SEL_24M) in rv1103b_peri_get_clk()
174 u32 sel, con; in rv1103b_i2c_get_clk() local
184 sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT; in rv1103b_i2c_get_clk()
[all …]
H A Dclk_rv1126b.c78 u32 con, sel, rate; in rv1126b_peri_get_clk() local
83 sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT; in rv1126b_peri_get_clk()
84 if (sel == ACLK_PERI_SEL_200M) in rv1126b_peri_get_clk()
91 sel = (con & PCLK_PERI_SEL_MASK) >> PCLK_PERI_SEL_SHIFT; in rv1126b_peri_get_clk()
92 if (sel == PCLK_PERI_SEL_100M) in rv1126b_peri_get_clk()
99 sel = (con & ACLK_TOP_SEL_MASK) >> ACLK_TOP_SEL_SHIFT; in rv1126b_peri_get_clk()
100 if (sel == ACLK_TOP_SEL_600M) in rv1126b_peri_get_clk()
102 else if (sel == ACLK_TOP_SEL_400M) in rv1126b_peri_get_clk()
114 sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT; in rv1126b_peri_get_clk()
115 if (sel == ACLK_BUS_SEL_400M) in rv1126b_peri_get_clk()
[all …]
H A Dclk_rk3528.c327 u32 sel, div, mask, shift, con; in rk3528_cgpll_matrix_get_rate() local
413 sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift; in rk3528_cgpll_matrix_get_rate()
414 if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO in rk3528_cgpll_matrix_get_rate()
435 u32 sel, div, mask, shift, con; in rk3528_cgpll_matrix_set_rate() local
522 sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO in rk3528_cgpll_matrix_set_rate()
525 sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX; in rk3528_cgpll_matrix_set_rate()
543 rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift); in rk3528_cgpll_matrix_set_rate()
551 u32 id, sel, con, mask, shift; in rk3528_i2c_get_clk() local
613 sel = (con & mask) >> shift; in rk3528_i2c_get_clk()
614 if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC) in rk3528_i2c_get_clk()
[all …]
H A Dclk_rk3588.c154 u32 con, sel, rate; in rk3588_center_get_clk() local
159 sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
161 if (sel == ACLK_CENTER_ROOT_SEL_700M) in rk3588_center_get_clk()
163 else if (sel == ACLK_CENTER_ROOT_SEL_400M) in rk3588_center_get_clk()
165 else if (sel == ACLK_CENTER_ROOT_SEL_200M) in rk3588_center_get_clk()
172 sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
174 if (sel == ACLK_CENTER_LOW_ROOT_SEL_500M) in rk3588_center_get_clk()
176 else if (sel == ACLK_CENTER_LOW_ROOT_SEL_250M) in rk3588_center_get_clk()
178 else if (sel == ACLK_CENTER_LOW_ROOT_SEL_100M) in rk3588_center_get_clk()
185 sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
[all …]
H A Dclk_rv1126.c264 u32 div, sel, con; in rv1126_pwm_get_pmuclk() local
269 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rv1126_pwm_get_pmuclk()
271 if (sel == CLK_PWM0_SEL_XIN24M) in rv1126_pwm_get_pmuclk()
276 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rv1126_pwm_get_pmuclk()
278 if (sel == CLK_PWM1_SEL_XIN24M) in rv1126_pwm_get_pmuclk()
623 u32 con, div, sel, parent; in rv1126_pdbus_get_clk() local
629 sel = (con & ACLK_PDBUS_SEL_MASK) >> ACLK_PDBUS_SEL_SHIFT; in rv1126_pdbus_get_clk()
630 if (sel == ACLK_PDBUS_SEL_GPLL) in rv1126_pdbus_get_clk()
632 else if (sel == ACLK_PDBUS_SEL_CPLL) in rv1126_pdbus_get_clk()
640 sel = (con & HCLK_PDBUS_SEL_MASK) >> HCLK_PDBUS_SEL_SHIFT; in rv1126_pdbus_get_clk()
[all …]
H A Dclk_rk3568.c287 u32 div, sel, con, parent; in rk3568_pwm_get_pmuclk() local
292 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rk3568_pwm_get_pmuclk()
294 if (sel == CLK_PWM0_SEL_XIN24M) in rk3568_pwm_get_pmuclk()
339 u32 div, con, sel, parent; in rk3568_pmu_get_pmuclk() local
342 sel = (con & PCLK_PDPMU_SEL_MASK) >> PCLK_PDPMU_SEL_SHIFT; in rk3568_pmu_get_pmuclk()
344 if (sel) in rk3568_pmu_get_pmuclk()
739 u32 con, sel, rate; in rk3568_bus_get_clk() local
744 sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT; in rk3568_bus_get_clk()
745 if (sel == ACLK_BUS_SEL_200M) in rk3568_bus_get_clk()
747 else if (sel == ACLK_BUS_SEL_150M) in rk3568_bus_get_clk()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dclock.c641 unsigned int sel; in exynos4_get_pwm_clk() local
649 sel = readl(&clk->src_peril0); in exynos4_get_pwm_clk()
650 sel = (sel >> 24) & 0xf; in exynos4_get_pwm_clk()
652 if (sel == 0x6) in exynos4_get_pwm_clk()
654 else if (sel == 0x7) in exynos4_get_pwm_clk()
656 else if (sel == 0x8) in exynos4_get_pwm_clk()
698 unsigned int sel; in exynos4_get_uart_clk() local
710 sel = readl(&clk->src_peril0); in exynos4_get_uart_clk()
711 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_uart_clk()
713 if (sel == 0x6) in exynos4_get_uart_clk()
[all …]
/rk3399_rockchip-uboot/drivers/power/regulator/
H A Drk801_regulator.c225 unsigned int sel; in regulator_map_voltage_linear_range() local
235 ret = linear_range_get_selector_high(range, min_uV, &sel, in regulator_map_voltage_linear_range()
240 ret = sel; in regulator_map_voltage_linear_range()
247 desc->n_linear_ranges, sel, &voltage)) in regulator_map_voltage_linear_range()
313 int sel, val, vsel_reg, ret; in rk801_regulator_get_value() local
331 sel = (val & desc->vsel_mask) >> (ffs(desc->vsel_mask) - 1); in rk801_regulator_get_value()
333 desc->n_linear_ranges, sel, &uV); in rk801_regulator_get_value()
336 __func__, dev->name, desc->id, vsel_reg, ret, sel, sel, uV); in rk801_regulator_get_value()
347 uint reg, reg0, reg1, sel; in rk801_regulator_set_value() local
363 sel = regulator_map_voltage_linear_range(desc, uV, uV); in rk801_regulator_set_value()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c97 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
121 if (selector_exists(&cd->sel)) { in peri_clk_enable()
122 reg = readl(base + cd->sel.offset); in peri_clk_enable()
123 bitfield_replace(reg, cd->sel.shift, cd->sel.width, in peri_clk_enable()
124 c->sel); in peri_clk_enable()
125 writel(reg, base + cd->sel.offset); in peri_clk_enable()
192 c->sel = i; in peri_clk_set_rate()
200 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
216 if (selector_exists(&cd->sel)) { in peri_clk_get_rate()
217 reg = readl(base + cd->sel.offset); in peri_clk_get_rate()
[all …]
H A Dclk-bcm281xx.c151 .sel = SELECTOR(0x0a28, 0, 3),
163 .sel = SELECTOR(0x0a2c, 0, 3),
175 .sel = SELECTOR(0x0a34, 0, 3),
187 .sel = SELECTOR(0x0a30, 0, 3),
240 .sel = SELECTOR(0x0a64, 0, 3),
251 .sel = SELECTOR(0x0a68, 0, 3),
262 .sel = SELECTOR(0x0a84, 0, 3),
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c97 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
121 if (selector_exists(&cd->sel)) { in peri_clk_enable()
122 reg = readl(base + cd->sel.offset); in peri_clk_enable()
123 bitfield_replace(reg, cd->sel.shift, cd->sel.width, in peri_clk_enable()
124 c->sel); in peri_clk_enable()
125 writel(reg, base + cd->sel.offset); in peri_clk_enable()
192 c->sel = i; in peri_clk_set_rate()
200 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
216 if (selector_exists(&cd->sel)) { in peri_clk_get_rate()
217 reg = readl(base + cd->sel.offset); in peri_clk_get_rate()
[all …]
H A Dclk-bcm235xx.c151 .sel = SELECTOR(0x0a28, 0, 3),
163 .sel = SELECTOR(0x0a2c, 0, 3),
175 .sel = SELECTOR(0x0a34, 0, 3),
187 .sel = SELECTOR(0x0a30, 0, 3),
240 .sel = SELECTOR(0x0a64, 0, 3),
251 .sel = SELECTOR(0x0a68, 0, 3),
262 .sel = SELECTOR(0x0a84, 0, 3),
/rk3399_rockchip-uboot/drivers/net/phy/
H A Drockchip-fephy.c126 int sel; in rockchip_fephy_config_init() local
129 sel = rockchip_fephy_group_read(phydev, GROUP_AFE, 0x3); in rockchip_fephy_config_init()
130 if (sel < 0) in rockchip_fephy_config_init()
131 return sel; in rockchip_fephy_config_init()
132 ret = rockchip_fephy_group_write(phydev, GROUP_AFE, 0x3, sel | 0x2); in rockchip_fephy_config_init()
/rk3399_rockchip-uboot/drivers/input/
H A Dps2mult.c72 static void ps2mult_send_byte(u_char byte, u_char sel) in ps2mult_send_byte() argument
74 ps2ser_putc(sel); in ps2mult_send_byte()
76 if (sel == PS2MULT_KB_SELECTOR) { in ps2mult_send_byte()
100 static void ps2mult_receive_byte(u_char byte, u_char sel) in ps2mult_receive_byte() argument
105 if (sel == PS2MULT_MS_SELECTOR) return; in ps2mult_receive_byte()
108 if (sel == PS2MULT_KB_SELECTOR) { in ps2mult_receive_byte()
/rk3399_rockchip-uboot/arch/mips/include/asm/
H A Dmipsregs.h913 #define __read_32bit_c0_register(source, sel) \ argument
915 if (sel == 0) \
922 "mfc0\t%0, " #source ", " #sel "\n\t" \
928 #define __read_64bit_c0_register(source, sel) \ argument
931 __res = __read_64bit_c0_split(source, sel); \
932 else if (sel == 0) \
941 "dmfc0\t%0, " #source ", " #sel "\n\t" \
947 #define __write_32bit_c0_register(register, sel, value) \ argument
949 if (sel == 0) \
956 "mtc0\t%z0, " #register ", " #sel "\n\t" \
[all …]
/rk3399_rockchip-uboot/scripts/
H A Dget_maintainer.pl1581 my $sel = "";
1582 $sel = "*" if ($selected{$count});
1589 printf STDERR "%1s %2d %-65s", $sel, $count + 1, $email;
1654 my $sel = substr($nr, 0, 1);
1659 if ($sel eq "y") {
1667 } elsif ($sel eq "*" || $sel eq '^') {
1669 $toggle = 1 if ($sel eq '*');
1673 } elsif ($sel eq "0") {
1677 } elsif ($sel eq "t") {
1699 } elsif ($sel eq "a") {
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dcpu.c235 struct clk_pll_table *sel; in init_pllx() local
255 sel = &tegra_pll_x_table[chip_sku][osc]; in init_pllx()
256 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); in init_pllx()
/rk3399_rockchip-uboot/arch/arm/mach-kirkwood/
H A Dmpp.c54 unsigned int sel = MPP_SEL(*mpp_list); in kirkwood_mpp_conf() local
78 mpp_ctrl[num / 8] |= sel << shift; in kirkwood_mpp_conf()
/rk3399_rockchip-uboot/arch/mips/cpu/
H A Dstart.S39 .macro init_wr sel argument
40 MTC0 zero, CP0_WATCHLO,\sel
41 mtc0 t1, CP0_WATCHHI,\sel
42 mfc0 t0, CP0_WATCHHI,\sel
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Dtve.h77 #define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4)) argument
/rk3399_rockchip-uboot/board/freescale/ls1043ardb/
H A Dls1043ardb_pbi.cfg9 #USB PHY frequency sel

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