65 	u32 con, sel, div, rate, prate;  in rv1103b_peri_get_clk()  local
70 		sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT;  in rv1103b_peri_get_clk()
71 		if (sel == ACLK_PERI_SEL_600M)  in rv1103b_peri_get_clk()
73 		else if (sel == ACLK_PERI_SEL_480M)  in rv1103b_peri_get_clk()
80 		sel = (con & LSCLK_PERI_SEL_MASK) >> LSCLK_PERI_SEL_SHIFT;  in rv1103b_peri_get_clk()
81 		if (sel == LSCLK_PERI_SEL_300M)  in rv1103b_peri_get_clk()
98 		sel = (con & LSCLK_PMU_SEL_MASK) >> LSCLK_PMU_SEL_SHIFT;  in rv1103b_peri_get_clk()
100 		if (sel == LSCLK_PMU_SEL_24M)  in rv1103b_peri_get_clk()
174 	u32 sel, con;  in rv1103b_i2c_get_clk()  local
184 		sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT;  in rv1103b_i2c_get_clk()
189 		sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT;  in rv1103b_i2c_get_clk()
195 	if (sel == CLK_I2C_SEL_100M)  in rv1103b_i2c_get_clk()
206 	u32 sel, con, rate;  in rv1103b_crypto_get_clk()  local
216 		sel = (con & CLK_CORE_CRYPTO_SEL_MASK) >>  in rv1103b_crypto_get_clk()
221 		sel = (con & CLK_PKA_CRYPTO_SEL_MASK) >>  in rv1103b_crypto_get_clk()
227 	if (sel == CLK_CORE_CRYPTO_SEL_300M)  in rv1103b_crypto_get_clk()
229 	else if (sel == CLK_CORE_CRYPTO_SEL_200M)  in rv1103b_crypto_get_clk()
242 	u32 sel;  in rv1103b_crypto_set_clk()  local
245 		sel = CLK_CORE_CRYPTO_SEL_300M;  in rv1103b_crypto_set_clk()
247 		sel = CLK_CORE_CRYPTO_SEL_200M;  in rv1103b_crypto_set_clk()
249 		sel = CLK_CORE_CRYPTO_SEL_100M;  in rv1103b_crypto_set_clk()
260 			     (sel << CLK_CORE_CRYPTO_SEL_SHIFT));  in rv1103b_crypto_set_clk()
265 			     (sel << CLK_PKA_CRYPTO_SEL_SHIFT));  in rv1103b_crypto_set_clk()
276 	u32 div, sel, con, prate;  in rv1103b_mmc_get_clk()  local
282 		sel = (con & CLK_SDMMC_SEL_MASK) >>  in rv1103b_mmc_get_clk()
286 		if (sel == CLK_MMC_SEL_GPLL)  in rv1103b_mmc_get_clk()
294 		sel = (con & CLK_SDMMC_SEL_MASK) >>  in rv1103b_mmc_get_clk()
298 		if (sel == CLK_MMC_SEL_GPLL)  in rv1103b_mmc_get_clk()
306 		sel = (con & CLK_EMMC_SEL_MASK) >>  in rv1103b_mmc_get_clk()
310 		if (sel == CLK_MMC_SEL_GPLL)  in rv1103b_mmc_get_clk()
318 		sel = (con & CLK_SFC_SEL_MASK) >>  in rv1103b_mmc_get_clk()
322 		if (sel == CLK_MMC_SEL_GPLL)  in rv1103b_mmc_get_clk()
336 	u32 sel, src_clk_div;  in rv1103b_mmc_set_clk()  local
340 		sel = CLK_MMC_SEL_OSC;  in rv1103b_mmc_set_clk()
343 		sel = CLK_MMC_SEL_GPLL;  in rv1103b_mmc_set_clk()
355 			     (sel << CLK_SDMMC_SEL_SHIFT) |  in rv1103b_mmc_set_clk()
365 			     (sel << CLK_SDMMC_SEL_SHIFT) |  in rv1103b_mmc_set_clk()
375 			     (sel << CLK_EMMC_SEL_SHIFT) |  in rv1103b_mmc_set_clk()
385 			     (sel << CLK_SFC_SEL_SHIFT) |  in rv1103b_mmc_set_clk()
429 	u32 sel, con, rate;  in rv1103b_spi_get_clk()  local
434 		sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;  in rv1103b_spi_get_clk()
439 	if (sel == CLK_SPI0_SEL_200M)  in rv1103b_spi_get_clk()
441 	else if (sel == CLK_SPI0_SEL_100M)  in rv1103b_spi_get_clk()
443 	else if (sel == CLK_SPI0_SEL_50M)  in rv1103b_spi_get_clk()
481 	u32 sel, con;  in rv1103b_pwm_get_clk()  local
487 		sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;  in rv1103b_pwm_get_clk()
491 		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;  in rv1103b_pwm_get_clk()
495 		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;  in rv1103b_pwm_get_clk()
501 	switch (sel) {  in rv1103b_pwm_get_clk()
769 	u32 sel, con, prate;  in rv1103b_decom_get_clk()  local
772 	sel = (con & DCLK_DECOM_SEL_MASK) >>  in rv1103b_decom_get_clk()
774 	if (sel == DCLK_DECOM_SEL_480M)  in rv1103b_decom_get_clk()
776 	else if (sel == DCLK_DECOM_SEL_400M)  in rv1103b_decom_get_clk()
786 	u32 sel;  in rv1103b_decom_set_clk()  local
789 		sel = DCLK_DECOM_SEL_480M;  in rv1103b_decom_set_clk()
791 		sel = DCLK_DECOM_SEL_400M;  in rv1103b_decom_set_clk()
793 		sel = DCLK_DECOM_SEL_300M;  in rv1103b_decom_set_clk()
795 		     (sel << DCLK_DECOM_SEL_SHIFT));  in rv1103b_decom_set_clk()