Lines Matching refs:sel
172 u32 con, sel, div, rate; in rk3576_bus_get_clk() local
177 sel = (con & ACLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
181 if (sel == ACLK_BUS_ROOT_SEL_CPLL) in rk3576_bus_get_clk()
188 sel = (con & HCLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
190 if (sel == HCLK_BUS_ROOT_SEL_200M) in rk3576_bus_get_clk()
192 else if (sel == HCLK_BUS_ROOT_SEL_100M) in rk3576_bus_get_clk()
194 else if (sel == HCLK_BUS_ROOT_SEL_50M) in rk3576_bus_get_clk()
201 sel = (con & PCLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
203 if (sel == PCLK_BUS_ROOT_SEL_100M) in rk3576_bus_get_clk()
205 else if (sel == PCLK_BUS_ROOT_SEL_50M) in rk3576_bus_get_clk()
278 u32 con, sel, div, rate, prate; in rk3576_top_get_clk() local
285 sel = (con & ACLK_TOP_SEL_MASK) >> in rk3576_top_get_clk()
287 if (sel == ACLK_TOP_SEL_CPLL) in rk3576_top_get_clk()
289 else if (sel == ACLK_TOP_SEL_AUPLL) in rk3576_top_get_clk()
298 sel = (con & ACLK_TOP_MID_SEL_MASK) >> in rk3576_top_get_clk()
300 if (sel == ACLK_TOP_MID_SEL_CPLL) in rk3576_top_get_clk()
307 sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT; in rk3576_top_get_clk()
308 if (sel == PCLK_TOP_SEL_100M) in rk3576_top_get_clk()
310 else if (sel == PCLK_TOP_SEL_50M) in rk3576_top_get_clk()
317 sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT; in rk3576_top_get_clk()
318 if (sel == HCLK_TOP_SEL_200M) in rk3576_top_get_clk()
320 else if (sel == HCLK_TOP_SEL_100M) in rk3576_top_get_clk()
322 else if (sel == HCLK_TOP_SEL_50M) in rk3576_top_get_clk()
407 u32 sel, con; in rk3576_i2c_get_clk() local
413 sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT; in rk3576_i2c_get_clk()
417 sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT; in rk3576_i2c_get_clk()
421 sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT; in rk3576_i2c_get_clk()
425 sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT; in rk3576_i2c_get_clk()
429 sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT; in rk3576_i2c_get_clk()
433 sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT; in rk3576_i2c_get_clk()
437 sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT; in rk3576_i2c_get_clk()
441 sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT; in rk3576_i2c_get_clk()
445 sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT; in rk3576_i2c_get_clk()
449 sel = (con & CLK_I2C9_SEL_MASK) >> CLK_I2C9_SEL_SHIFT; in rk3576_i2c_get_clk()
455 if (sel == CLK_I2C_SEL_200M) in rk3576_i2c_get_clk()
457 else if (sel == CLK_I2C_SEL_100M) in rk3576_i2c_get_clk()
459 else if (sel == CLK_I2C_SEL_50M) in rk3576_i2c_get_clk()
532 u32 sel, con; in rk3576_spi_get_clk() local
537 sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT; in rk3576_spi_get_clk()
541 sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT; in rk3576_spi_get_clk()
545 sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT; in rk3576_spi_get_clk()
549 sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT; in rk3576_spi_get_clk()
553 sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT; in rk3576_spi_get_clk()
559 switch (sel) { in rk3576_spi_get_clk()
624 u32 sel, con; in rk3576_pwm_get_clk() local
629 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3576_pwm_get_clk()
633 sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; in rk3576_pwm_get_clk()
637 sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT; in rk3576_pwm_get_clk()
643 switch (sel) { in rk3576_pwm_get_clk()
694 u32 div, sel, con, prate; in rk3576_adc_get_clk() local
700 sel = (con & CLK_SARADC_SEL_MASK) >> in rk3576_adc_get_clk()
702 if (sel == CLK_SARADC_SEL_OSC) in rk3576_adc_get_clk()
765 u32 sel, con, prate, div = 0; in rk3576_mmc_get_clk() local
772 sel = (con & CCLK_SDIO_SRC_SEL_MASK) >> in rk3576_mmc_get_clk()
774 if (sel == CCLK_SDIO_SRC_SEL_GPLL) in rk3576_mmc_get_clk()
776 else if (sel == CCLK_SDIO_SRC_SEL_CPLL) in rk3576_mmc_get_clk()
785 sel = (con & CCLK_SDMMC0_SRC_SEL_MASK) >> in rk3576_mmc_get_clk()
787 if (sel == CCLK_SDMMC0_SRC_SEL_GPLL) in rk3576_mmc_get_clk()
789 else if (sel == CCLK_SDMMC0_SRC_SEL_CPLL) in rk3576_mmc_get_clk()
798 sel = (con & CCLK_EMMC_SEL_MASK) >> in rk3576_mmc_get_clk()
800 if (sel == CCLK_EMMC_SEL_GPLL) in rk3576_mmc_get_clk()
802 else if (sel == CCLK_EMMC_SEL_CPLL) in rk3576_mmc_get_clk()
809 sel = (con & BCLK_EMMC_SEL_MASK) >> in rk3576_mmc_get_clk()
811 if (sel == BCLK_EMMC_SEL_200M) in rk3576_mmc_get_clk()
813 else if (sel == BCLK_EMMC_SEL_100M) in rk3576_mmc_get_clk()
815 else if (sel == BCLK_EMMC_SEL_50M) in rk3576_mmc_get_clk()
823 sel = (con & SCLK_FSPI_SEL_MASK) >> in rk3576_mmc_get_clk()
825 if (sel == SCLK_FSPI_SEL_GPLL) in rk3576_mmc_get_clk()
827 else if (sel == SCLK_FSPI_SEL_CPLL) in rk3576_mmc_get_clk()
835 sel = (con & SCLK_FSPI_SEL_MASK) >> in rk3576_mmc_get_clk()
837 if (sel == SCLK_FSPI_SEL_GPLL) in rk3576_mmc_get_clk()
839 else if (sel == SCLK_FSPI_SEL_CPLL) in rk3576_mmc_get_clk()
847 sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT; in rk3576_mmc_get_clk()
848 if (sel == DCLK_DECOM_SEL_SPLL) in rk3576_mmc_get_clk()
972 u32 div, sel, con, parent = 0; in rk3576_aclk_vop_get_clk() local
979 sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
980 if (sel == ACLK_VOP_ROOT_SEL_GPLL) in rk3576_aclk_vop_get_clk()
982 else if (sel == ACLK_VOP_ROOT_SEL_CPLL) in rk3576_aclk_vop_get_clk()
984 else if (sel == ACLK_VOP_ROOT_SEL_AUPLL) in rk3576_aclk_vop_get_clk()
986 else if (sel == ACLK_VOP_ROOT_SEL_SPLL) in rk3576_aclk_vop_get_clk()
988 else if (sel == ACLK_VOP_ROOT_SEL_LPLL) in rk3576_aclk_vop_get_clk()
994 sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
995 if (sel == ACLK_VO0_ROOT_SEL_GPLL) in rk3576_aclk_vop_get_clk()
997 else if (sel == ACLK_VO0_ROOT_SEL_CPLL) in rk3576_aclk_vop_get_clk()
999 else if (sel == ACLK_VO0_ROOT_SEL_LPLL) in rk3576_aclk_vop_get_clk()
1001 else if (sel == ACLK_VO0_ROOT_SEL_BPLL) in rk3576_aclk_vop_get_clk()
1007 sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
1008 if (sel == ACLK_VO0_ROOT_SEL_GPLL) in rk3576_aclk_vop_get_clk()
1010 else if (sel == ACLK_VO0_ROOT_SEL_CPLL) in rk3576_aclk_vop_get_clk()
1012 else if (sel == ACLK_VO0_ROOT_SEL_LPLL) in rk3576_aclk_vop_get_clk()
1014 else if (sel == ACLK_VO0_ROOT_SEL_BPLL) in rk3576_aclk_vop_get_clk()
1019 sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
1020 if (sel == HCLK_VOP_ROOT_SEL_200M) in rk3576_aclk_vop_get_clk()
1022 else if (sel == HCLK_VOP_ROOT_SEL_100M) in rk3576_aclk_vop_get_clk()
1024 else if (sel == HCLK_VOP_ROOT_SEL_50M) in rk3576_aclk_vop_get_clk()
1030 sel = (con & PCLK_VOP_ROOT_SEL_MASK) >> PCLK_VOP_ROOT_SEL_SHIFT; in rk3576_aclk_vop_get_clk()
1031 if (sel == PCLK_VOP_ROOT_SEL_100M) in rk3576_aclk_vop_get_clk()
1033 else if (sel == PCLK_VOP_ROOT_SEL_50M) in rk3576_aclk_vop_get_clk()
1131 u32 div, sel, con, parent; in rk3576_dclk_vop_get_clk() local
1138 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_get_clk()
1144 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_get_clk()
1150 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_get_clk()
1156 if (sel == DCLK_VOP_SRC_SEL_VPLL) in rk3576_dclk_vop_get_clk()
1158 else if (sel == DCLK_VOP_SRC_SEL_BPLL) in rk3576_dclk_vop_get_clk()
1160 else if (sel == DCLK_VOP_SRC_SEL_LPLL) in rk3576_dclk_vop_get_clk()
1162 else if (sel == DCLK_VOP_SRC_SEL_GPLL) in rk3576_dclk_vop_get_clk()
1177 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; in rk3576_dclk_vop_set_clk() local
1185 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_set_clk()
1194 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_set_clk()
1203 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3576_dclk_vop_set_clk()
1212 if (sel == DCLK_VOP_SRC_SEL_VPLL) { in rk3576_dclk_vop_set_clk()
1286 u32 div, sel, con, parent; in rk3576_clk_csihost_get_clk() local
1292 sel = (con & CLK_DSIHOST0_SEL_MASK) >> CLK_DSIHOST0_SEL_SHIFT; in rk3576_clk_csihost_get_clk()
1298 if (sel == CLK_DSIHOST0_SEL_VPLL) in rk3576_clk_csihost_get_clk()
1300 else if (sel == CLK_DSIHOST0_SEL_BPLL) in rk3576_clk_csihost_get_clk()
1302 else if (sel == CLK_DSIHOST0_SEL_LPLL) in rk3576_clk_csihost_get_clk()
1304 else if (sel == CLK_DSIHOST0_SEL_GPLL) in rk3576_clk_csihost_get_clk()
1306 else if (sel == CLK_DSIHOST0_SEL_SPLL) in rk3576_clk_csihost_get_clk()
1384 u32 div, sel, con, parent; in rk3576_dclk_ebc_get_clk() local
1391 sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT; in rk3576_dclk_ebc_get_clk()
1392 if (sel == DCLK_EBC_SEL_CPLL) in rk3576_dclk_ebc_get_clk()
1394 else if (sel == DCLK_EBC_SEL_VPLL) in rk3576_dclk_ebc_get_clk()
1396 else if (sel == DCLK_EBC_SEL_AUPLL) in rk3576_dclk_ebc_get_clk()
1398 else if (sel == DCLK_EBC_SEL_LPLL) in rk3576_dclk_ebc_get_clk()
1400 else if (sel == DCLK_EBC_SEL_GPLL) in rk3576_dclk_ebc_get_clk()
1402 else if (sel == DCLK_EBC_SEL_FRAC_SRC) in rk3576_dclk_ebc_get_clk()
1410 sel = (con & DCLK_EBC_FRAC_SRC_SEL_MASK) >> DCLK_EBC_FRAC_SRC_SEL_SHIFT; in rk3576_dclk_ebc_get_clk()
1411 if (sel == DCLK_EBC_FRAC_SRC_SEL_GPLL) in rk3576_dclk_ebc_get_clk()
1413 else if (sel == DCLK_EBC_FRAC_SRC_SEL_CPLL) in rk3576_dclk_ebc_get_clk()
1415 else if (sel == DCLK_EBC_FRAC_SRC_SEL_VPLL) in rk3576_dclk_ebc_get_clk()
1417 else if (sel == DCLK_EBC_FRAC_SRC_SEL_AUPLL) in rk3576_dclk_ebc_get_clk()
1437 u32 i, con, sel, div, best_div = 0, best_sel = 0; in rk3576_dclk_ebc_set_clk() local
1443 sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT; in rk3576_dclk_ebc_set_clk()
1444 if (sel == DCLK_EBC_SEL_VPLL) { in rk3576_dclk_ebc_set_clk()
1468 } else if (sel == DCLK_EBC_SEL_FRAC_SRC) { in rk3576_dclk_ebc_set_clk()
1524 sel = DCLK_EBC_FRAC_SRC_SEL_GPLL; in rk3576_dclk_ebc_set_clk()
1546 (sel << DCLK_EBC_FRAC_SRC_SEL_SHIFT)); in rk3576_dclk_ebc_set_clk()
2390 u32 sel; in rk3576_dclk_vop_set_parent() local
2394 sel = 2; in rk3576_dclk_vop_set_parent()
2396 sel = 0; in rk3576_dclk_vop_set_parent()
2398 sel = 1; in rk3576_dclk_vop_set_parent()
2400 sel = 3; in rk3576_dclk_vop_set_parent()
2402 sel = 4; in rk3576_dclk_vop_set_parent()
2407 sel << DCLK0_VOP_SRC_SEL_SHIFT); in rk3576_dclk_vop_set_parent()
2411 sel << DCLK0_VOP_SRC_SEL_SHIFT); in rk3576_dclk_vop_set_parent()
2415 sel << DCLK0_VOP_SRC_SEL_SHIFT); in rk3576_dclk_vop_set_parent()
2419 sel = 1; in rk3576_dclk_vop_set_parent()
2421 sel = 0; in rk3576_dclk_vop_set_parent()
2423 sel << DCLK0_VOP_SEL_SHIFT); in rk3576_dclk_vop_set_parent()
2427 sel = 1; in rk3576_dclk_vop_set_parent()
2429 sel = 0; in rk3576_dclk_vop_set_parent()
2431 sel << DCLK1_VOP_SEL_SHIFT); in rk3576_dclk_vop_set_parent()
2435 sel = 1; in rk3576_dclk_vop_set_parent()
2437 sel = 0; in rk3576_dclk_vop_set_parent()
2439 sel << DCLK2_VOP_SEL_SHIFT); in rk3576_dclk_vop_set_parent()
2443 sel = 0; in rk3576_dclk_vop_set_parent()
2445 sel = 1; in rk3576_dclk_vop_set_parent()
2447 sel = 2; in rk3576_dclk_vop_set_parent()
2449 sel = 3; in rk3576_dclk_vop_set_parent()
2451 sel = 4; in rk3576_dclk_vop_set_parent()
2453 sel = 5; in rk3576_dclk_vop_set_parent()
2455 sel = 6; in rk3576_dclk_vop_set_parent()
2457 sel << DCLK_EBC_SEL_SHIFT); in rk3576_dclk_vop_set_parent()
2470 u32 sel; in rk3576_ufs_ref_set_parent() local
2474 sel = 2; in rk3576_ufs_ref_set_parent()
2476 sel = 0; in rk3576_ufs_ref_set_parent()
2478 sel = 1; in rk3576_ufs_ref_set_parent()
2480 rk_clrsetreg(&cru->pmuclksel_con[3], 0x3, sel << 0); in rk3576_ufs_ref_set_parent()