mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before

mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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Merge git://git.denx.de/u-boot-mips

MIPS: Stop building position independent code

U-Boot has up until now built with -fpic for the MIPS architecture,
producing position independent code which uses indirection through a
global offset t

MIPS: Stop building position independent code

U-Boot has up until now built with -fpic for the MIPS architecture,
producing position independent code which uses indirection through a
global offset table, making relocation fairly straightforward as it
simply involves patching up GOT entries.

Using -fpic does however have some downsides. The biggest of these is
that generated code is bloated in various ways. For example, function
calls are indirected through the GOT & the t9 register:

8f998064 lw t9,-32668(gp)
0320f809 jalr t9

Without -fpic the call is simply:

0f803f01 jal be00fc04 <puts>

This is more compact & faster (due to the lack of the load & the
dependency the jump has on its result). It is also easier to read &
debug because the disassembly shows what function is being called,
rather than just an offset from gp which would then have to be looked up
in the ELF to discover the target function.

Another disadvantage of -fpic is that each function begins with a
sequence to calculate the value of the gp register, for example:

3c1c0004 lui gp,0x4
279c3384 addiu gp,gp,13188
0399e021 addu gp,gp,t9

Without using -fpic this sequence no longer appears at the start of each
function, reducing code size considerably.

This patch switches U-Boot from building with -fpic to building with
-fno-pic, in order to gain the benefits described above. The cost of
this is an extra step during the build process to extract relocation
data from the ELF & write it into a new .rel section in a compact
format, plus the added complexity of dealing with multiple types of
relocation rather than the single type that applied to the GOT. The
benefit is smaller, cleaner, more debuggable code. The relocate_code()
function is reimplemented in C to handle the new relocation scheme,
which also makes it easier to read & debug.

Taking maltael_defconfig as an example the size of u-boot.bin built
using the Codescape MIPS 2016.05-06 toolchain (gcc 4.9.2, binutils
2.24.90) shrinks from 254KiB to 224KiB.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mips

MIPS: add initial infrastructure for Broadcom MIPS SoCs

CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez

MIPS: add initial infrastructure for Broadcom MIPS SoCs

CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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MIPS: call debug_uart_init right before board_init_f

All MIPS boards that support debug uart are calling debug_uart_init right at
the beginning of board_early_init_f.
Instead of doing that, let's pr

MIPS: call debug_uart_init right before board_init_f

All MIPS boards that support debug uart are calling debug_uart_init right at
the beginning of board_early_init_f.
Instead of doing that, let's provide a generic call to debug_uart_init right
before the call to board_init_f if debug uart is enabled for boards without
stack in SRAM.
On the other hand, boards with stack in SRAM can call earlier (right before
low level init).

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mips

MIPS: add possibility to setup initial stack and global data in SRAM

This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together w

MIPS: add possibility to setup initial stack and global data in SRAM

This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together with
CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be
set up in that SRAM. This can be used to provide a C environment
also for lowlevel_init().

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

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MIPS: factor out code for initial stack and global data

Move the code for setting up the initial stack and global data
to a macro to be able to use it more than once.

Signed-off-by: Daniel Schwierz

MIPS: factor out code for initial stack and global data

Move the code for setting up the initial stack and global data
to a macro to be able to use it more than once.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

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MIPS: fix iand optimize setup of CP0 registers

Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exc

MIPS: fix iand optimize setup of CP0 registers

Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.

Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.

Initialize cp0 count as early as possible to get the most
accurate boot timing.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

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MIPS: fix ROM exception vectors

When booting from ROM, early exceptions can't be handled
properly. Instead of busy-looping give the developer the
possibilty to examine the situation. Invoke an UHI
e

MIPS: fix ROM exception vectors

When booting from ROM, early exceptions can't be handled
properly. Instead of busy-looping give the developer the
possibilty to examine the situation. Invoke an UHI
exception operation which can be read as unhandled exception
by a hardware debugger if one is attached. If the debugger
doesn't support UHI, the exception is read as unexpected
breakpoint.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

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MIPS: make inclusion of ROM exception vectors configurable

This adds a compile time option to include code for static
exception vectors. Static exception vectors are only needed,
when the U-Boot ent

MIPS: make inclusion of ROM exception vectors configurable

This adds a compile time option to include code for static
exception vectors. Static exception vectors are only needed,
when the U-Boot entry point is equal to the CPU reset exception
vector address. For instance this is the case when U-Boot is
used as ROM in Qemu or booted from parallel NOR flash. When
U-Boot is booted from RAM (e.g. loaded there by SPL), the
exception vectors need to be setup dynamically, which is done
in follow-up commits.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mips

MIPS: Hang if run on a secondary CPU

Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on mul

MIPS: Hang if run on a secondary CPU

Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on multiple CPUs simultaneously, which causes all sorts of
issues as the multiple instances of U-Boot clobber each other.

Prevent this from happening by simply hanging with an infinite loop if
we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum
as appropriate, is non-zero.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

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MIPS: Fix cache maintenance in relocate_code & simplify

The relocate_code function was handling cache maintenance incorrectly.
It copied U-Boot to its new location, flushed the caches & then
proceed

MIPS: Fix cache maintenance in relocate_code & simplify

The relocate_code function was handling cache maintenance incorrectly.
It copied U-Boot to its new location, flushed the caches & then
proceeded to apply relocations & jump to the new code without flushing
the caches again. This is problematic as the instruction cache could
potentially have already fetched instructions that hadn't had relocs
applied.

Rework this to perform the flush_cache call using the code in the
original copy of U-Boot, after having applied relocations to the new
copy of U-Boot. The new U-Boot can then be jumped to safely once that
cache flush has been performed.

As part of this, since the old U-Boot is used up until after that cache
flush, complexity around loading values from the GOT using a jump & link
instruction & loads from a table is removed. Instead we can simply load
the needed values with PTR_LA fromt the original GOT.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

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MIPS: Ensure Config.K0=2 applies before any memory accesses

During boot we set Config.K0=2 (uncached) such that any accesses to the
kseg0 memory region are performed uncached before the caches are
i

MIPS: Ensure Config.K0=2 applies before any memory accesses

During boot we set Config.K0=2 (uncached) such that any accesses to the
kseg0 memory region are performed uncached before the caches are
initialised. This write to the Config register introduces an execution
hazard between it & any following memory accesses (such as the load of
_gp), which we need to clear in order to ensure those memory accesses
are actually performed uncached. Clear this execution hazard with the
insertion of an ehb execution hazard barrier instruction.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

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MIPS: Map CM Global Control Registers

Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul

MIPS: Map CM Global Control Registers

Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

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MIPS: If we don't need DDR for cache init, init cache first

On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)

MIPS: If we don't need DDR for cache init, init cache first

On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
perform cache initialisation prior to lowlevel_init & DDR
initialisation. This allows for DDR initialisation code to run cached &
thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

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MIPS: Preserve Config implementation-defined bits

The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other fu

MIPS: Preserve Config implementation-defined bits

The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS architecture.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

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MIPS: Enable use of the instruction cache earlier

Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rat

MIPS: Enable use of the instruction cache earlier

Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Merge branch 'master' of git://git.denx.de/u-boot-mips

MIPS: Use unchecked immediate addition/subtraction

In MIPS assembly there have historically been 2 variants of immediate
addition - the standard "addi" which traps if an overflow occurs, and
the unc

MIPS: Use unchecked immediate addition/subtraction

In MIPS assembly there have historically been 2 variants of immediate
addition - the standard "addi" which traps if an overflow occurs, and
the unchecked "addiu" which does not trap on overflow. In release 6 of
the MIPS architecture the trapping variants of immediate addition &
subtraction have been removed. In preparation for supporting MIPSr6,
stop using the trapping instructions from assembly & switch to their
unchecked variants.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

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Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging

Use correct spelling of "U-Boot"

Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed

Use correct spelling of "U-Boot"

Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>

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