154 	u32 con, sel, rate;  in rk3588_center_get_clk()  local
159 		sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >>  in rk3588_center_get_clk()
161 		if (sel == ACLK_CENTER_ROOT_SEL_700M)  in rk3588_center_get_clk()
163 		else if (sel == ACLK_CENTER_ROOT_SEL_400M)  in rk3588_center_get_clk()
165 		else if (sel == ACLK_CENTER_ROOT_SEL_200M)  in rk3588_center_get_clk()
172 		sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >>  in rk3588_center_get_clk()
174 		if (sel == ACLK_CENTER_LOW_ROOT_SEL_500M)  in rk3588_center_get_clk()
176 		else if (sel == ACLK_CENTER_LOW_ROOT_SEL_250M)  in rk3588_center_get_clk()
178 		else if (sel == ACLK_CENTER_LOW_ROOT_SEL_100M)  in rk3588_center_get_clk()
185 		sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >>  in rk3588_center_get_clk()
187 		if (sel == HCLK_CENTER_ROOT_SEL_400M)  in rk3588_center_get_clk()
189 		else if (sel == HCLK_CENTER_ROOT_SEL_200M)  in rk3588_center_get_clk()
191 		else if (sel == HCLK_CENTER_ROOT_SEL_100M)  in rk3588_center_get_clk()
198 		sel = (con & PCLK_CENTER_ROOT_SEL_MASK) >>  in rk3588_center_get_clk()
200 		if (sel == PCLK_CENTER_ROOT_SEL_200M)  in rk3588_center_get_clk()
202 		else if (sel == PCLK_CENTER_ROOT_SEL_100M)  in rk3588_center_get_clk()
204 		else if (sel == PCLK_CENTER_ROOT_SEL_50M)  in rk3588_center_get_clk()
286 	u32 con, sel, div, rate, prate;  in rk3588_top_get_clk()  local
293 		sel = (con & ACLK_TOP_ROOT_SRC_SEL_MASK) >>  in rk3588_top_get_clk()
295 		if (sel == ACLK_TOP_ROOT_SRC_SEL_CPLL)  in rk3588_top_get_clk()
304 		sel = (con & ACLK_LOW_TOP_ROOT_SRC_SEL_MASK) >>  in rk3588_top_get_clk()
306 		if (sel == ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL)  in rk3588_top_get_clk()
313 		sel = (con & PCLK_TOP_ROOT_SEL_MASK) >> PCLK_TOP_ROOT_SEL_SHIFT;  in rk3588_top_get_clk()
314 		if (sel == PCLK_TOP_ROOT_SEL_100M)  in rk3588_top_get_clk()
316 		else if (sel == PCLK_TOP_ROOT_SEL_50M)  in rk3588_top_get_clk()
383 	u32 sel, con;  in rk3588_i2c_get_clk()  local
389 		sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT;  in rk3588_i2c_get_clk()
393 		sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT;  in rk3588_i2c_get_clk()
397 		sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT;  in rk3588_i2c_get_clk()
401 		sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT;  in rk3588_i2c_get_clk()
405 		sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT;  in rk3588_i2c_get_clk()
409 		sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT;  in rk3588_i2c_get_clk()
413 		sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT;  in rk3588_i2c_get_clk()
417 		sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT;  in rk3588_i2c_get_clk()
421 		sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT;  in rk3588_i2c_get_clk()
426 	if (sel == CLK_I2C_SEL_200M)  in rk3588_i2c_get_clk()
492 	u32 sel, con;  in rk3588_spi_get_clk()  local
498 		sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;  in rk3588_spi_get_clk()
501 		sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;  in rk3588_spi_get_clk()
504 		sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;  in rk3588_spi_get_clk()
507 		sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;  in rk3588_spi_get_clk()
510 		sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT;  in rk3588_spi_get_clk()
516 	switch (sel) {  in rk3588_spi_get_clk()
577 	u32 sel, con;  in rk3588_pwm_get_clk()  local
582 		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;  in rk3588_pwm_get_clk()
586 		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;  in rk3588_pwm_get_clk()
590 		sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;  in rk3588_pwm_get_clk()
594 		sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT;  in rk3588_pwm_get_clk()
600 	switch (sel) {  in rk3588_pwm_get_clk()
656 	u32 div, sel, con, prate;  in rk3588_adc_get_clk()  local
662 		sel = (con & CLK_SARADC_SEL_MASK) >>  in rk3588_adc_get_clk()
664 		if (sel == CLK_SARADC_SEL_24M)  in rk3588_adc_get_clk()
673 		sel = (con & CLK_TSADC_SEL_MASK) >>  in rk3588_adc_get_clk()
675 		if (sel == CLK_TSADC_SEL_24M)  in rk3588_adc_get_clk()
747 	u32 sel, con, div, prate;  in rk3588_mmc_get_clk()  local
753 		sel = (con & CCLK_SDIO_SRC_SEL_MASK) >>  in rk3588_mmc_get_clk()
755 		if (sel == CCLK_SDIO_SRC_SEL_GPLL)  in rk3588_mmc_get_clk()
757 		else if (sel == CCLK_SDIO_SRC_SEL_CPLL)  in rk3588_mmc_get_clk()
765 		sel = (con & CCLK_EMMC_SEL_MASK) >>  in rk3588_mmc_get_clk()
767 		if (sel == CCLK_EMMC_SEL_GPLL)  in rk3588_mmc_get_clk()
769 		else if (sel == CCLK_EMMC_SEL_CPLL)  in rk3588_mmc_get_clk()
777 		sel = (con & BCLK_EMMC_SEL_MASK) >>  in rk3588_mmc_get_clk()
779 		if (sel == CCLK_EMMC_SEL_CPLL)  in rk3588_mmc_get_clk()
787 		sel = (con & SCLK_SFC_SEL_MASK) >>  in rk3588_mmc_get_clk()
789 		if (sel == SCLK_SFC_SEL_GPLL)  in rk3588_mmc_get_clk()
791 		else if (sel == SCLK_SFC_SEL_CPLL)  in rk3588_mmc_get_clk()
799 		sel = (con & DCLK_DECOM_SEL_MASK) >>  in rk3588_mmc_get_clk()
801 		if (sel == DCLK_DECOM_SEL_SPLL)  in rk3588_mmc_get_clk()
950 	u32 div, sel, con, parent;  in rk3588_aclk_vop_get_clk()  local
957 		sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT;  in rk3588_aclk_vop_get_clk()
958 		if (sel == ACLK_VOP_ROOT_SEL_GPLL)  in rk3588_aclk_vop_get_clk()
960 		else if (sel == ACLK_VOP_ROOT_SEL_CPLL)  in rk3588_aclk_vop_get_clk()
962 		else if (sel == ACLK_VOP_ROOT_SEL_AUPLL)  in rk3588_aclk_vop_get_clk()
964 		else if (sel == ACLK_VOP_ROOT_SEL_NPLL)  in rk3588_aclk_vop_get_clk()
971 		sel = (con & ACLK_VOP_LOW_ROOT_SEL_MASK) >>  in rk3588_aclk_vop_get_clk()
973 		if (sel == ACLK_VOP_LOW_ROOT_SEL_400M)  in rk3588_aclk_vop_get_clk()
975 		else if (sel == ACLK_VOP_LOW_ROOT_SEL_200M)  in rk3588_aclk_vop_get_clk()
977 		else if (sel == ACLK_VOP_LOW_ROOT_SEL_100M)  in rk3588_aclk_vop_get_clk()
983 		sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT;  in rk3588_aclk_vop_get_clk()
984 		if (sel == HCLK_VOP_ROOT_SEL_200M)  in rk3588_aclk_vop_get_clk()
986 		else if (sel == HCLK_VOP_ROOT_SEL_100M)  in rk3588_aclk_vop_get_clk()
988 		else if (sel == HCLK_VOP_ROOT_SEL_50M)  in rk3588_aclk_vop_get_clk()
1064 	u32 div, sel, con, parent;  in rk3588_dclk_vop_get_clk()  local
1071 		sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_get_clk()
1077 		sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_get_clk()
1083 		sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_get_clk()
1088 		sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_get_clk()
1094 	if (sel == DCLK_VOP_SRC_SEL_AUPLL)  in rk3588_dclk_vop_get_clk()
1096 	else if (sel == DCLK_VOP_SRC_SEL_V0PLL)  in rk3588_dclk_vop_get_clk()
1099 	else if (sel == DCLK_VOP_SRC_SEL_GPLL)  in rk3588_dclk_vop_get_clk()
1114 	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;  in rk3588_dclk_vop_set_clk()  local
1122 		sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_set_clk()
1131 		sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_set_clk()
1140 		sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_set_clk()
1148 		sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_set_clk()
1157 	if (sel == DCLK_VOP_SRC_SEL_V0PLL) {  in rk3588_dclk_vop_set_clk()
1226 	u32 div, sel, con, parent;  in rk3588_clk_csihost_get_clk()  local
1240 	sel = (con & CLK_DSIHOST_SEL_MASK) >> CLK_DSIHOST_SEL_SHIFT;  in rk3588_clk_csihost_get_clk()
1242 	if (sel == CLK_DSIHOST_SEL_GPLL)  in rk3588_clk_csihost_get_clk()
1244 	else if (sel == CLK_DSIHOST_SEL_CPLL)  in rk3588_clk_csihost_get_clk()
1246 	else if (sel == CLK_DSIHOST_SEL_V0PLL)  in rk3588_clk_csihost_get_clk()
1966 	u32 sel;  in rk3588_dclk_vop_set_parent()  local
1970 		sel = 2;  in rk3588_dclk_vop_set_parent()
1972 		sel = 0;  in rk3588_dclk_vop_set_parent()
1974 		sel = 1;  in rk3588_dclk_vop_set_parent()
1976 		sel = 3;  in rk3588_dclk_vop_set_parent()
1981 			     sel << DCLK0_VOP_SRC_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1985 			     sel << DCLK1_VOP_SRC_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1989 			     sel << DCLK2_VOP_SRC_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1993 			     sel << DCLK3_VOP_SRC_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1997 			sel = 1;  in rk3588_dclk_vop_set_parent()
1999 			sel = 2;  in rk3588_dclk_vop_set_parent()
2001 			sel = 0;  in rk3588_dclk_vop_set_parent()
2003 			     sel << DCLK0_VOP_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
2007 			sel = 1;  in rk3588_dclk_vop_set_parent()
2009 			sel = 2;  in rk3588_dclk_vop_set_parent()
2011 			sel = 0;  in rk3588_dclk_vop_set_parent()
2013 			     sel << DCLK1_VOP_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
2017 			sel = 1;  in rk3588_dclk_vop_set_parent()
2019 			sel = 2;  in rk3588_dclk_vop_set_parent()
2021 			sel = 0;  in rk3588_dclk_vop_set_parent()
2023 			     sel << DCLK2_VOP_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()