264 	u32 div, sel, con;  in rv1126_pwm_get_pmuclk()  local
269 		sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;  in rv1126_pwm_get_pmuclk()
271 		if (sel == CLK_PWM0_SEL_XIN24M)  in rv1126_pwm_get_pmuclk()
276 		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;  in rv1126_pwm_get_pmuclk()
278 		if (sel == CLK_PWM1_SEL_XIN24M)  in rv1126_pwm_get_pmuclk()
623 	u32 con, div, sel, parent;  in rv1126_pdbus_get_clk()  local
629 		sel = (con & ACLK_PDBUS_SEL_MASK) >> ACLK_PDBUS_SEL_SHIFT;  in rv1126_pdbus_get_clk()
630 		if (sel == ACLK_PDBUS_SEL_GPLL)  in rv1126_pdbus_get_clk()
632 		else if (sel == ACLK_PDBUS_SEL_CPLL)  in rv1126_pdbus_get_clk()
640 		sel = (con & HCLK_PDBUS_SEL_MASK) >> HCLK_PDBUS_SEL_SHIFT;  in rv1126_pdbus_get_clk()
641 		if (sel == HCLK_PDBUS_SEL_GPLL)  in rv1126_pdbus_get_clk()
643 		else if (sel == HCLK_PDBUS_SEL_CPLL)  in rv1126_pdbus_get_clk()
652 		sel = (con & PCLK_PDBUS_SEL_MASK) >> PCLK_PDBUS_SEL_SHIFT;  in rv1126_pdbus_get_clk()
653 		if (sel == PCLK_PDBUS_SEL_GPLL)  in rv1126_pdbus_get_clk()
655 		else if (sel == PCLK_PDBUS_SEL_CPLL)  in rv1126_pdbus_get_clk()
883 	u32 div, sel, con;  in rv1126_pwm_get_clk()  local
886 	sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;  in rv1126_pwm_get_clk()
888 	if (sel == CLK_PWM2_SEL_XIN24M)  in rv1126_pwm_get_clk()
942 	u32 div, sel, con, parent;  in rv1126_crypto_get_clk()  local
948 		sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >> CLK_CRYPTO_CORE_SEL_SHIFT;  in rv1126_crypto_get_clk()
949 		if (sel == CLK_CRYPTO_CORE_SEL_GPLL)  in rv1126_crypto_get_clk()
951 		else if (sel == CLK_CRYPTO_CORE_SEL_CPLL)  in rv1126_crypto_get_clk()
959 		sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >> CLK_CRYPTO_PKA_SEL_SHIFT;  in rv1126_crypto_get_clk()
960 		if (sel == CLK_CRYPTO_PKA_SEL_GPLL)  in rv1126_crypto_get_clk()
962 		else if (sel == CLK_CRYPTO_PKA_SEL_CPLL)  in rv1126_crypto_get_clk()
970 		sel = (con & ACLK_CRYPTO_SEL_MASK) >> ACLK_CRYPTO_SEL_SHIFT;  in rv1126_crypto_get_clk()
971 		if (sel == ACLK_CRYPTO_SEL_GPLL)  in rv1126_crypto_get_clk()
973 		else if (sel == ACLK_CRYPTO_SEL_CPLL)  in rv1126_crypto_get_clk()
1027 	u32 div, sel, con, con_id;  in rv1126_mmc_get_clk()  local
1049 	sel = (con & EMMC_SEL_MASK) >> EMMC_SEL_SHIFT;  in rv1126_mmc_get_clk()
1050 	if (sel == EMMC_SEL_GPLL)  in rv1126_mmc_get_clk()
1052 	else if (sel == EMMC_SEL_CPLL)  in rv1126_mmc_get_clk()
1054 	else if (sel == EMMC_SEL_XIN24M)  in rv1126_mmc_get_clk()
1108 	u32 div, sel, con, parent;  in rv1126_sfc_get_clk()  local
1112 	sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT;  in rv1126_sfc_get_clk()
1113 	if (sel == SCLK_SFC_SEL_GPLL)  in rv1126_sfc_get_clk()
1115 	else if (sel == SCLK_SFC_SEL_CPLL)  in rv1126_sfc_get_clk()
1140 	u32 div, sel, con, parent;  in rv1126_nand_get_clk()  local
1144 	sel = (con & CLK_NANDC_SEL_MASK) >> CLK_NANDC_SEL_SHIFT;  in rv1126_nand_get_clk()
1145 	if (sel == CLK_NANDC_SEL_GPLL)  in rv1126_nand_get_clk()
1147 	else if (sel == CLK_NANDC_SEL_CPLL)  in rv1126_nand_get_clk()
1172 	u32 div, sel, con, parent;  in rv1126_aclk_vop_get_clk()  local
1176 	sel = (con & ACLK_PDVO_SEL_MASK) >> ACLK_PDVO_SEL_SHIFT;  in rv1126_aclk_vop_get_clk()
1177 	if (sel == ACLK_PDVO_SEL_GPLL)  in rv1126_aclk_vop_get_clk()
1179 	else if (sel == ACLK_PDVO_SEL_CPLL)  in rv1126_aclk_vop_get_clk()
1205 	u32 div, sel, con, parent;  in rv1126_dclk_vop_get_clk()  local
1209 	sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT;  in rv1126_dclk_vop_get_clk()
1210 	if (sel == DCLK_VOP_SEL_GPLL)  in rv1126_dclk_vop_get_clk()
1212 	else if (sel == DCLK_VOP_SEL_CPLL)  in rv1126_dclk_vop_get_clk()
1269 	u32 div, sel, con, parent;  in rv1126_scr1_get_clk()  local
1273 	sel = (con & CLK_SCR1_SEL_MASK) >> CLK_SCR1_SEL_SHIFT;  in rv1126_scr1_get_clk()
1274 	if (sel == CLK_SCR1_SEL_GPLL)  in rv1126_scr1_get_clk()
1276 	else if (sel == CLK_SCR1_SEL_CPLL)  in rv1126_scr1_get_clk()
1302 	u32 div, sel, con, parent;  in rv1126_gmac_src_get_clk()  local
1306 	sel = (con & CLK_GMAC_SRC_SEL_MASK) >> CLK_GMAC_SRC_SEL_SHIFT;  in rv1126_gmac_src_get_clk()
1307 	if (sel == CLK_GMAC_SRC_SEL_CPLL)  in rv1126_gmac_src_get_clk()
1309 	else if (sel == CLK_GMAC_SRC_SEL_GPLL)  in rv1126_gmac_src_get_clk()
1335 	u32 div, sel, con, parent;  in rv1126_gmac_out_get_clk()  local
1339 	sel = (con & CLK_GMAC_OUT_SEL_MASK) >> CLK_GMAC_OUT_SEL_SHIFT;  in rv1126_gmac_out_get_clk()
1340 	if (sel == CLK_GMAC_OUT_SEL_CPLL)  in rv1126_gmac_out_get_clk()
1342 	else if (sel == CLK_GMAC_OUT_SEL_GPLL)  in rv1126_gmac_out_get_clk()
1368 	u32 con, sel, div_sel;  in rv1126_gmac_tx_rx_set_clk()  local
1371 	sel = (con & GMAC_MODE_SEL_MASK) >> GMAC_MODE_SEL_SHIFT;  in rv1126_gmac_tx_rx_set_clk()
1373 	if (sel == GMAC_RGMII_MODE) {  in rv1126_gmac_tx_rx_set_clk()
1382 	} else if (sel == GMAC_RMII_MODE) {  in rv1126_gmac_tx_rx_set_clk()
1411 	u32 div, fracdiv, sel, con, n, m, parent = priv->gpll_hz;  in rv1126_clk_mipicsi_out_get_clk()  local
1415 	sel = (con & MIPICSI_OUT_SEL_MASK) >> MIPICSI_OUT_SEL_SHIFT;  in rv1126_clk_mipicsi_out_get_clk()
1416 	if (sel == MIPICSI_OUT_SEL_XIN24M) {  in rv1126_clk_mipicsi_out_get_clk()
1418 	} else if (sel == MIPICSI_OUT_SEL_FRACDIV) {  in rv1126_clk_mipicsi_out_get_clk()
1460 	u32 div, sel, con, parent, con_id;  in rv1126_clk_pdvi_ispp_get_clk()  local
1478 	sel = (con & ACLK_PDVI_SEL_MASK) >> ACLK_PDVI_SEL_SHIFT;  in rv1126_clk_pdvi_ispp_get_clk()
1479 	if (sel == ACLK_PDVI_SEL_GPLL)  in rv1126_clk_pdvi_ispp_get_clk()
1481 	else if (sel == ACLK_PDVI_SEL_CPLL)  in rv1126_clk_pdvi_ispp_get_clk()
1483 	else if (sel == ACLK_PDVI_SEL_HPLL)  in rv1126_clk_pdvi_ispp_get_clk()
1495 	u32 parent, sel, src_clk_div, con_id;  in rv1126_clk_pdvi_ispp_set_clk()  local
1513 		sel = ACLK_PDVI_SEL_CPLL;  in rv1126_clk_pdvi_ispp_set_clk()
1516 		sel = ACLK_PDVI_SEL_HPLL;  in rv1126_clk_pdvi_ispp_set_clk()
1519 		sel = ACLK_PDVI_SEL_GPLL;  in rv1126_clk_pdvi_ispp_set_clk()
1526 		     sel << ACLK_PDVI_SEL_SHIFT |  in rv1126_clk_pdvi_ispp_set_clk()
1535 	u32 div, sel, con, parent;  in rv1126_clk_isp_get_clk()  local
1539 	sel = (con & CLK_ISP_SEL_MASK) >> CLK_ISP_SEL_SHIFT;  in rv1126_clk_isp_get_clk()
1540 	if (sel == CLK_ISP_SEL_GPLL)  in rv1126_clk_isp_get_clk()
1542 	else if (sel == CLK_ISP_SEL_CPLL)  in rv1126_clk_isp_get_clk()
1544 	else if (sel == CLK_ISP_SEL_HPLL)  in rv1126_clk_isp_get_clk()
1555 	u32 parent, sel, src_clk_div;  in rv1126_clk_isp_set_clk()  local
1559 		sel = CLK_ISP_SEL_CPLL;  in rv1126_clk_isp_set_clk()
1562 		sel = CLK_ISP_SEL_HPLL;  in rv1126_clk_isp_set_clk()
1565 		sel = CLK_ISP_SEL_GPLL;  in rv1126_clk_isp_set_clk()
1572 		     sel << CLK_ISP_SEL_SHIFT |  in rv1126_clk_isp_set_clk()
1582 	u32 div, sel, con, parent;  in rv1126_dclk_decom_get_clk()  local
1586 	sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT;  in rv1126_dclk_decom_get_clk()
1587 	if (sel == DCLK_DECOM_SEL_GPLL)  in rv1126_dclk_decom_get_clk()
1589 	else if (sel == DCLK_DECOM_SEL_CPLL)  in rv1126_dclk_decom_get_clk()