Lines Matching refs:sel
78 u32 con, sel, rate; in rv1126b_peri_get_clk() local
83 sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT; in rv1126b_peri_get_clk()
84 if (sel == ACLK_PERI_SEL_200M) in rv1126b_peri_get_clk()
91 sel = (con & PCLK_PERI_SEL_MASK) >> PCLK_PERI_SEL_SHIFT; in rv1126b_peri_get_clk()
92 if (sel == PCLK_PERI_SEL_100M) in rv1126b_peri_get_clk()
99 sel = (con & ACLK_TOP_SEL_MASK) >> ACLK_TOP_SEL_SHIFT; in rv1126b_peri_get_clk()
100 if (sel == ACLK_TOP_SEL_600M) in rv1126b_peri_get_clk()
102 else if (sel == ACLK_TOP_SEL_400M) in rv1126b_peri_get_clk()
114 sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT; in rv1126b_peri_get_clk()
115 if (sel == ACLK_BUS_SEL_400M) in rv1126b_peri_get_clk()
117 else if (sel == ACLK_BUS_SEL_300M) in rv1126b_peri_get_clk()
124 sel = (con & HCLK_BUS_SEL_MASK) >> HCLK_BUS_SEL_SHIFT; in rv1126b_peri_get_clk()
125 if (sel == HCLK_BUS_SEL_200M) in rv1126b_peri_get_clk()
208 u32 sel, con; in rv1126b_i2c_get_clk() local
219 sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT; in rv1126b_i2c_get_clk()
220 if (sel == CLK_I2C_SEL_200M) in rv1126b_i2c_get_clk()
227 sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT; in rv1126b_i2c_get_clk()
228 if (sel == CLK_I2C2_SEL_100M) in rv1126b_i2c_get_clk()
230 else if (sel == CLK_I2C2_SEL_RCOSC) in rv1126b_i2c_get_clk()
281 u32 sel, con, rate; in rv1126b_crypto_get_clk() local
291 sel = (con & ACLK_RKCE_SEL_MASK) >> in rv1126b_crypto_get_clk()
293 if (sel == ACLK_RKCE_SEL_200M) in rv1126b_crypto_get_clk()
301 sel = (con & CLK_PKA_RKCE_SEL_MASK) >> in rv1126b_crypto_get_clk()
303 if (sel == CLK_PKA_RKCE_SEL_300M) in rv1126b_crypto_get_clk()
318 u32 sel; in rv1126b_crypto_set_clk() local
328 sel = ACLK_RKCE_SEL_200M; in rv1126b_crypto_set_clk()
330 sel = ACLK_RKCE_SEL_24M; in rv1126b_crypto_set_clk()
333 (sel << ACLK_RKCE_SEL_SHIFT)); in rv1126b_crypto_set_clk()
338 sel = CLK_PKA_RKCE_SEL_300M; in rv1126b_crypto_set_clk()
340 sel = CLK_PKA_RKCE_SEL_200M; in rv1126b_crypto_set_clk()
343 (sel << CLK_PKA_RKCE_SEL_SHIFT)); in rv1126b_crypto_set_clk()
354 u32 div, sel, con, prate; in rv1126b_mmc_get_clk() local
360 sel = (con & CLK_SDMMC_SEL_MASK) >> in rv1126b_mmc_get_clk()
364 if (sel == CLK_SDMMC_SEL_GPLL) in rv1126b_mmc_get_clk()
366 else if (sel == CLK_SDMMC_SEL_CPLL) in rv1126b_mmc_get_clk()
374 sel = (con & CLK_SDMMC_SEL_MASK) >> in rv1126b_mmc_get_clk()
378 if (sel == CLK_SDMMC_SEL_GPLL) in rv1126b_mmc_get_clk()
380 else if (sel == CLK_SDMMC_SEL_CPLL) in rv1126b_mmc_get_clk()
388 sel = (con & CLK_SDMMC_SEL_MASK) >> in rv1126b_mmc_get_clk()
392 if (sel == CLK_SDMMC_SEL_GPLL) in rv1126b_mmc_get_clk()
394 else if (sel == CLK_SDMMC_SEL_CPLL) in rv1126b_mmc_get_clk()
403 sel = (con & CLK_SDMMC_SEL_MASK) >> in rv1126b_mmc_get_clk()
407 if (sel == CLK_SDMMC_SEL_GPLL) in rv1126b_mmc_get_clk()
409 else if (sel == CLK_SDMMC_SEL_CPLL) in rv1126b_mmc_get_clk()
418 sel = (con & SCLK_1X_FSPI1_SEL_MASK) >> in rv1126b_mmc_get_clk()
422 if (sel == SCLK_1X_FSPI1_SEL_100M) in rv1126b_mmc_get_clk()
424 else if (sel == SCLK_1X_FSPI1_SEL_RCOSC) in rv1126b_mmc_get_clk()
438 u32 sel, src_clk_div; in rv1126b_mmc_set_clk() local
442 sel = CLK_SDMMC_SEL_24M; in rv1126b_mmc_set_clk()
445 sel = CLK_SDMMC_SEL_CPLL; in rv1126b_mmc_set_clk()
448 sel = CLK_SDMMC_SEL_GPLL; in rv1126b_mmc_set_clk()
460 (sel << CLK_SDMMC_SEL_SHIFT) | in rv1126b_mmc_set_clk()
470 (sel << CLK_SDMMC_SEL_SHIFT) | in rv1126b_mmc_set_clk()
480 (sel << CLK_SDMMC_SEL_SHIFT) | in rv1126b_mmc_set_clk()
491 (sel << CLK_SDMMC_SEL_SHIFT) | in rv1126b_mmc_set_clk()
499 sel = SCLK_1X_FSPI1_SEL_24M; in rv1126b_mmc_set_clk()
502 sel = SCLK_1X_FSPI1_SEL_100M; in rv1126b_mmc_set_clk()
505 sel = SCLK_1X_FSPI1_SEL_RCOSC; in rv1126b_mmc_set_clk()
512 (sel << SCLK_1X_FSPI1_SEL_SHIFT) | in rv1126b_mmc_set_clk()
525 u32 sel, con, rate; in rv1126b_spi_get_clk() local
530 sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT; in rv1126b_spi_get_clk()
534 sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT; in rv1126b_spi_get_clk()
539 if (sel == CLK_SPI0_SEL_200M) in rv1126b_spi_get_clk()
541 else if (sel == CLK_SPI0_SEL_100M) in rv1126b_spi_get_clk()
543 else if (sel == CLK_SPI0_SEL_50M) in rv1126b_spi_get_clk()
585 u32 sel, div, con; in rv1126b_pwm_get_clk() local
590 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rv1126b_pwm_get_clk()
594 sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; in rv1126b_pwm_get_clk()
598 sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT; in rv1126b_pwm_get_clk()
602 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rv1126b_pwm_get_clk()
605 if (sel == CLK_PWM1_SEL_100M) in rv1126b_pwm_get_clk()
607 else if (sel == CLK_PWM1_SEL_RCOSC) in rv1126b_pwm_get_clk()
615 switch (sel) { in rv1126b_pwm_get_clk()
682 u32 sel, div, con; in rv1126b_adc_get_clk() local
688 sel = (con & CLK_SARADC0_SEL_MASK) >> CLK_SARADC0_SEL_SHIFT; in rv1126b_adc_get_clk()
695 sel = (con & CLK_SARADC1_SEL_MASK) >> CLK_SARADC1_SEL_SHIFT; in rv1126b_adc_get_clk()
702 sel = (con & CLK_SARADC2_SEL_MASK) >> CLK_SARADC2_SEL_SHIFT; in rv1126b_adc_get_clk()
713 if (sel == CLK_SARADC_SEL_200M) in rv1126b_adc_get_clk()
1235 u32 sel, con; in rv1126b_wdt_get_rate() local
1241 sel = (con & TCLK_WDT_NS_SEL_MASK) >> in rv1126b_wdt_get_rate()
1246 sel = (con & TCLK_WDT_S_SEL_MASK) >> in rv1126b_wdt_get_rate()
1251 sel = (con & TCLK_WDT_HPMCU_SEL_MASK) >> in rv1126b_wdt_get_rate()
1256 sel = (con & TCLK_WDT_LPMCU_SEL_MASK) >> in rv1126b_wdt_get_rate()
1258 if (sel == TCLK_WDT_LPMCU_SEL_100M) in rv1126b_wdt_get_rate()
1260 else if (sel == TCLK_WDT_LPMCU_SEL_RCOSC) in rv1126b_wdt_get_rate()
1262 else if (sel == TCLK_WDT_LPMCU_SEL_OSC) in rv1126b_wdt_get_rate()
1270 if (sel == TCLK_WDT_SEL_100M) in rv1126b_wdt_get_rate()
1325 u32 sel, div, con, p_rate; in rv1126b_vop_get_rate() local
1330 sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT; in rv1126b_vop_get_rate()
1336 if (sel == DCLK_VOP_SEL_CPLL) in rv1126b_vop_get_rate()
1375 u32 sel, div, con, p_rate; in rv1126b_mac_get_rate() local
1381 sel = (con & CLK_GMAC_PTP_REF_SRC_SEL_MASK) >> in rv1126b_mac_get_rate()
1385 if (sel == CLK_GMAC_PTP_REF_SRC_SEL_CPLL) in rv1126b_mac_get_rate()
1392 sel = (con & CLK_MAC_OUT2IO_SEL_MASK) >> in rv1126b_mac_get_rate()
1396 if (sel == CLK_MAC_OUT2IO_SEL_CPLL) in rv1126b_mac_get_rate()
1398 else if (sel == CLK_MAC_OUT2IO_SEL_GPLL) in rv1126b_mac_get_rate()