287 	u32 div, sel, con, parent;  in rk3568_pwm_get_pmuclk()  local
292 		sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT;  in rk3568_pwm_get_pmuclk()
294 		if (sel == CLK_PWM0_SEL_XIN24M)  in rk3568_pwm_get_pmuclk()
339 	u32 div, con, sel, parent;  in rk3568_pmu_get_pmuclk()  local
342 	sel = (con & PCLK_PDPMU_SEL_MASK) >> PCLK_PDPMU_SEL_SHIFT;  in rk3568_pmu_get_pmuclk()
344 	if (sel)  in rk3568_pmu_get_pmuclk()
739 	u32 con, sel, rate;  in rk3568_bus_get_clk()  local
744 		sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT;  in rk3568_bus_get_clk()
745 		if (sel == ACLK_BUS_SEL_200M)  in rk3568_bus_get_clk()
747 		else if (sel == ACLK_BUS_SEL_150M)  in rk3568_bus_get_clk()
749 		else if (sel == ACLK_BUS_SEL_100M)  in rk3568_bus_get_clk()
757 		sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT;  in rk3568_bus_get_clk()
758 		if (sel == PCLK_BUS_SEL_100M)  in rk3568_bus_get_clk()
760 		else if (sel == PCLK_BUS_SEL_75M)  in rk3568_bus_get_clk()
762 		else if (sel == PCLK_BUS_SEL_50M)  in rk3568_bus_get_clk()
820 	u32 con, sel, rate;  in rk3568_perimid_get_clk()  local
825 		sel = (con & ACLK_PERIMID_SEL_MASK) >> ACLK_PERIMID_SEL_SHIFT;  in rk3568_perimid_get_clk()
826 		if (sel == ACLK_PERIMID_SEL_300M)  in rk3568_perimid_get_clk()
828 		else if (sel == ACLK_PERIMID_SEL_200M)  in rk3568_perimid_get_clk()
830 		else if (sel == ACLK_PERIMID_SEL_100M)  in rk3568_perimid_get_clk()
837 		sel = (con & HCLK_PERIMID_SEL_MASK) >> HCLK_PERIMID_SEL_SHIFT;  in rk3568_perimid_get_clk()
838 		if (sel == HCLK_PERIMID_SEL_150M)  in rk3568_perimid_get_clk()
840 		else if (sel == HCLK_PERIMID_SEL_100M)  in rk3568_perimid_get_clk()
842 		else if (sel == HCLK_PERIMID_SEL_75M)  in rk3568_perimid_get_clk()
899 	u32 con, sel, rate;  in rk3568_top_get_clk()  local
904 		sel = (con & ACLK_TOP_HIGH_SEL_MASK) >> ACLK_TOP_HIGH_SEL_SHIFT;  in rk3568_top_get_clk()
905 		if (sel == ACLK_TOP_HIGH_SEL_500M)  in rk3568_top_get_clk()
907 		else if (sel == ACLK_TOP_HIGH_SEL_400M)  in rk3568_top_get_clk()
909 		else if (sel == ACLK_TOP_HIGH_SEL_300M)  in rk3568_top_get_clk()
916 		sel = (con & ACLK_TOP_LOW_SEL_MASK) >> ACLK_TOP_LOW_SEL_SHIFT;  in rk3568_top_get_clk()
917 		if (sel == ACLK_TOP_LOW_SEL_400M)  in rk3568_top_get_clk()
919 		else if (sel == ACLK_TOP_LOW_SEL_300M)  in rk3568_top_get_clk()
921 		else if (sel == ACLK_TOP_LOW_SEL_200M)  in rk3568_top_get_clk()
928 		sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT;  in rk3568_top_get_clk()
929 		if (sel == HCLK_TOP_SEL_150M)  in rk3568_top_get_clk()
931 		else if (sel == HCLK_TOP_SEL_100M)  in rk3568_top_get_clk()
933 		else if (sel == HCLK_TOP_SEL_75M)  in rk3568_top_get_clk()
940 		sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT;  in rk3568_top_get_clk()
941 		if (sel == PCLK_TOP_SEL_100M)  in rk3568_top_get_clk()
943 		else if (sel == PCLK_TOP_SEL_75M)  in rk3568_top_get_clk()
945 		else if (sel == PCLK_TOP_SEL_50M)  in rk3568_top_get_clk()
1028 	u32 sel, con;  in rk3568_i2c_get_clk()  local
1038 		sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT;  in rk3568_i2c_get_clk()
1039 		if (sel == CLK_I2C_SEL_200M)  in rk3568_i2c_get_clk()
1041 		else if (sel == CLK_I2C_SEL_100M)  in rk3568_i2c_get_clk()
1043 		else if (sel == CLK_I2C_SEL_CPLL_100M)  in rk3568_i2c_get_clk()
1087 	u32 sel, con;  in rk3568_spi_get_clk()  local
1093 		sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;  in rk3568_spi_get_clk()
1096 		sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;  in rk3568_spi_get_clk()
1099 		sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;  in rk3568_spi_get_clk()
1102 		sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;  in rk3568_spi_get_clk()
1108 	switch (sel) {  in rk3568_spi_get_clk()
1164 	u32 sel, con;  in rk3568_pwm_get_clk()  local
1170 		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;  in rk3568_pwm_get_clk()
1173 		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;  in rk3568_pwm_get_clk()
1176 		sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;  in rk3568_pwm_get_clk()
1182 	switch (sel) {  in rk3568_pwm_get_clk()
1231 	u32 div, sel, con, prate;  in rk3568_adc_get_clk()  local
1240 		sel = (con & CLK_TSADC_TSEN_SEL_MASK) >>  in rk3568_adc_get_clk()
1242 		if (sel == CLK_TSADC_TSEN_SEL_24M)  in rk3568_adc_get_clk()
1307 	u32 sel, con;  in rk3568_crypto_get_rate()  local
1313 		sel = (con & ACLK_SECURE_FLASH_SEL_MASK) >>  in rk3568_crypto_get_rate()
1315 		if (sel == ACLK_SECURE_FLASH_SEL_200M)  in rk3568_crypto_get_rate()
1317 		else if (sel == ACLK_SECURE_FLASH_SEL_150M)  in rk3568_crypto_get_rate()
1319 		else if (sel == ACLK_SECURE_FLASH_SEL_100M)  in rk3568_crypto_get_rate()
1327 		sel = (con & HCLK_SECURE_FLASH_SEL_MASK) >>  in rk3568_crypto_get_rate()
1329 		if (sel == HCLK_SECURE_FLASH_SEL_150M)  in rk3568_crypto_get_rate()
1331 		else if (sel == HCLK_SECURE_FLASH_SEL_100M)  in rk3568_crypto_get_rate()
1333 		else if (sel == HCLK_SECURE_FLASH_SEL_75M)  in rk3568_crypto_get_rate()
1339 		sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >>  in rk3568_crypto_get_rate()
1341 		if (sel == CLK_CRYPTO_CORE_SEL_200M)  in rk3568_crypto_get_rate()
1343 		else if (sel == CLK_CRYPTO_CORE_SEL_150M)  in rk3568_crypto_get_rate()
1349 		sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >>  in rk3568_crypto_get_rate()
1351 		if (sel == CLK_CRYPTO_PKA_SEL_300M)  in rk3568_crypto_get_rate()
1353 		else if (sel == CLK_CRYPTO_PKA_SEL_200M)  in rk3568_crypto_get_rate()
1428 	u32 sel, con;  in rk3568_sdmmc_get_clk()  local
1434 		sel = (con & CLK_SDMMC0_SEL_MASK) >> CLK_SDMMC0_SEL_SHIFT;  in rk3568_sdmmc_get_clk()
1438 		sel = (con & CLK_SDMMC1_SEL_MASK) >> CLK_SDMMC1_SEL_SHIFT;  in rk3568_sdmmc_get_clk()
1442 		sel = (con & CLK_SDMMC2_SEL_MASK) >> CLK_SDMMC2_SEL_SHIFT;  in rk3568_sdmmc_get_clk()
1448 	switch (sel) {  in rk3568_sdmmc_get_clk()
1525 	u32 sel, con;  in rk3568_sfc_get_clk()  local
1528 	sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT;  in rk3568_sfc_get_clk()
1529 	switch (sel) {  in rk3568_sfc_get_clk()
1585 	u32 sel, con;  in rk3568_nand_get_clk()  local
1588 	sel = (con & NCLK_NANDC_SEL_MASK) >> NCLK_NANDC_SEL_SHIFT;  in rk3568_nand_get_clk()
1589 	switch (sel) {  in rk3568_nand_get_clk()
1635 	u32 sel, con;  in rk3568_emmc_get_clk()  local
1638 	sel = (con & CCLK_EMMC_SEL_MASK) >> CCLK_EMMC_SEL_SHIFT;  in rk3568_emmc_get_clk()
1639 	switch (sel) {  in rk3568_emmc_get_clk()
1697 	u32 sel, con;  in rk3568_emmc_get_bclk()  local
1700 	sel = (con & BCLK_EMMC_SEL_MASK) >> BCLK_EMMC_SEL_SHIFT;  in rk3568_emmc_get_bclk()
1701 	switch (sel) {  in rk3568_emmc_get_bclk()
1743 	u32 div, sel, con, parent;  in rk3568_aclk_vop_get_clk()  local
1747 	sel = (con & ACLK_VOP_PRE_SEL_MASK) >> ACLK_VOP_PRE_SEL_SHIFT;  in rk3568_aclk_vop_get_clk()
1748 	if (sel == ACLK_VOP_PRE_SEL_GPLL)  in rk3568_aclk_vop_get_clk()
1750 	else if (sel == ACLK_VOP_PRE_SEL_CPLL)  in rk3568_aclk_vop_get_clk()
1752 	else if (sel == ACLK_VOP_PRE_SEL_VPLL)  in rk3568_aclk_vop_get_clk()
1784 	u32 conid, div, sel, con, parent;  in rk3568_dclk_vop_get_clk()  local
1802 	sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;  in rk3568_dclk_vop_get_clk()
1803 	if (sel == DCLK_VOP_SEL_HPLL)  in rk3568_dclk_vop_get_clk()
1805 	else if (sel == DCLK_VOP_SEL_VPLL)  in rk3568_dclk_vop_get_clk()
1808 	else if (sel == DCLK_VOP_SEL_GPLL)  in rk3568_dclk_vop_get_clk()
1810 	else if (sel == DCLK_VOP_SEL_CPLL)  in rk3568_dclk_vop_get_clk()
1825 	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;  in rk3568_dclk_vop_set_clk()  local
1842 	sel = (con & DCLK0_VOP_SEL_MASK) >> DCLK0_VOP_SEL_SHIFT;  in rk3568_dclk_vop_set_clk()
1844 	if (sel == DCLK_VOP_SEL_HPLL) {  in rk3568_dclk_vop_set_clk()
1851 	} else if (sel == DCLK_VOP_SEL_VPLL) {  in rk3568_dclk_vop_set_clk()
1862 		for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) {  in rk3568_dclk_vop_set_clk()
1908 	u32 sel, con;  in rk3568_gmac_src_get_clk()  local
1911 	sel = (con & CLK_MAC0_2TOP_SEL_MASK) >> CLK_MAC0_2TOP_SEL_SHIFT;  in rk3568_gmac_src_get_clk()
1913 	switch (sel) {  in rk3568_gmac_src_get_clk()
1958 	u32 sel, con;  in rk3568_gmac_out_get_clk()  local
1961 	sel = (con & CLK_MAC0_OUT_SEL_MASK) >> CLK_MAC0_OUT_SEL_SHIFT;  in rk3568_gmac_out_get_clk()
1963 	switch (sel) {  in rk3568_gmac_out_get_clk()
2011 	u32 sel, con;  in rk3568_gmac_ptp_ref_get_clk()  local
2014 	sel = (con & CLK_GMAC0_PTP_REF_SEL_MASK) >> CLK_GMAC0_PTP_REF_SEL_SHIFT;  in rk3568_gmac_ptp_ref_get_clk()
2016 	switch (sel) {  in rk3568_gmac_ptp_ref_get_clk()
2064 	u32 con, sel, div_sel;  in rk3568_gmac_tx_rx_set_clk()  local
2067 	sel = (con & RMII0_MODE_MASK) >> RMII0_MODE_SHIFT;  in rk3568_gmac_tx_rx_set_clk()
2069 	if (sel == RMII0_MODE_SEL_RGMII) {  in rk3568_gmac_tx_rx_set_clk()
2079 	} else if (sel == RMII0_MODE_SEL_RMII) {  in rk3568_gmac_tx_rx_set_clk()