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Searched refs:pll_rate (Results 1 – 16 of 16) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dclock.c26 static unsigned pll_rate[CLOCK_ID_COUNT]; variable
275 div = clk_get_divider(8, pll_rate[clkid], rate); in clock_set_pllout()
314 unsigned parent_rate = pll_rate[parent]; in clock_get_periph_rate()
452 divider = find_best_divider(divider_bits, pll_rate[parent], in clock_adjust_periph_pll_div()
690 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); in clock_init()
691 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); in clock_init()
692 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); in clock_init()
693 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB); in clock_init()
694 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); in clock_init()
695 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); in clock_init()
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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1108.c146 ulong pll_rate; in rv1108_mac_set_clk() local
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
152 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
158 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
165 return DIV_TO_RATE(pll_rate, div); in rv1108_mac_set_clk()
171 u32 pll_rate; in rv1108_sfc_set_clk() local
175 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_sfc_set_clk()
177 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); in rv1108_sfc_set_clk()
179 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
186 return DIV_TO_RATE(pll_rate, div); in rv1108_sfc_set_clk()
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H A Dclk_rk3576.c1176 ulong pll_rate, now, best_rate = 0; in rk3576_dclk_vop_set_clk() local
1213 pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], in rk3576_dclk_vop_set_clk()
1215 if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { in rk3576_dclk_vop_set_clk()
1216 div = DIV_ROUND_UP(pll_rate, rate); in rk3576_dclk_vop_set_clk()
1238 pll_rate = priv->gpll_hz; in rk3576_dclk_vop_set_clk()
1241 pll_rate = priv->cpll_hz; in rk3576_dclk_vop_set_clk()
1244 pll_rate = 0; in rk3576_dclk_vop_set_clk()
1247 pll_rate = 0; in rk3576_dclk_vop_set_clk()
1250 pll_rate = 0; in rk3576_dclk_vop_set_clk()
1257 div = DIV_ROUND_UP(pll_rate, rate); in rk3576_dclk_vop_set_clk()
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H A Dclk_rk3308.c265 ulong pll_rate; in rk3308_mac_set_clk() local
269 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
272 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1], in rk3308_mac_set_clk()
275 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_mac_set_clk()
282 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk3308_mac_set_clk()
287 return DIV_TO_RATE(pll_rate, div); in rk3308_mac_set_clk()
564 ulong pll_rate, now, best_rate = 0; in rk3308_vop_set_clk() local
570 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
573 pll_rate = priv->vpll0_hz; in rk3308_vop_set_clk()
576 pll_rate = priv->vpll1_hz; in rk3308_vop_set_clk()
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H A Dclk_rk3328.c261 ulong pll_rate; in rk3328_gmac2io_set_clk() local
265 pll_rate = priv->gpll_hz; in rk3328_gmac2io_set_clk()
267 pll_rate = priv->cpll_hz; in rk3328_gmac2io_set_clk()
269 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2io_set_clk()
276 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2io_set_clk()
285 ulong pll_rate; in rk3328_gmac2phy_src_set_clk() local
289 pll_rate = GPLL_HZ; in rk3328_gmac2phy_src_set_clk()
291 pll_rate = CPLL_HZ; in rk3328_gmac2phy_src_set_clk()
293 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2phy_src_set_clk()
300 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2phy_src_set_clk()
H A Dclk_rk3368.c296 u32 pll_rate; in rk3368_mmc_get_clk() local
315 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
318 pll_rate = OSC_HZ; in rk3368_mmc_get_clk()
321 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
328 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
461 ulong pll_rate; in rk3368_gmac_set_clk() local
466 pll_rate = GPLL_HZ; in rk3368_gmac_set_clk()
469 pll_rate = CPLL_HZ; in rk3368_gmac_set_clk()
474 div = DIV_ROUND_UP(pll_rate, set_rate) - 1; in rk3368_gmac_set_clk()
481 return DIV_TO_RATE(pll_rate, div); in rk3368_gmac_set_clk()
H A Dclk_rk3588.c1113 ulong pll_rate, now, best_rate = 0; in rk3588_dclk_vop_set_clk() local
1158 pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_dclk_vop_set_clk()
1160 if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { in rk3588_dclk_vop_set_clk()
1161 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1181 pll_rate = priv->gpll_hz; in rk3588_dclk_vop_set_clk()
1184 pll_rate = priv->cpll_hz; in rk3588_dclk_vop_set_clk()
1187 pll_rate = priv->aupll_hz; in rk3588_dclk_vop_set_clk()
1190 pll_rate = 0; in rk3588_dclk_vop_set_clk()
1197 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1200 now = pll_rate / div; in rk3588_dclk_vop_set_clk()
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H A Dclk_rk1808.c599 ulong pll_rate; in rk1808_mac_set_clk() local
603 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL], in rk1808_mac_set_clk()
606 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[PPLL], in rk1808_mac_set_clk()
609 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], in rk1808_mac_set_clk()
616 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk1808_mac_set_clk()
621 return DIV_TO_RATE(pll_rate, div); in rk1808_mac_set_clk()
H A Dclk_rk3288.c449 ulong pll_rate; in rockchip_mac_set_clk() local
454 pll_rate = GPLL_HZ; in rockchip_mac_set_clk()
457 pll_rate = CPLL_HZ; in rockchip_mac_set_clk()
459 pll_rate = NPLL_HZ; in rockchip_mac_set_clk()
461 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
468 return DIV_TO_RATE(pll_rate, div); in rockchip_mac_set_clk()
H A Dclk_rk322x.c194 ulong pll_rate; in rk322x_mac_set_clk() local
198 pll_rate = priv->gpll_hz; in rk322x_mac_set_clk()
203 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rk322x_mac_set_clk()
210 return DIV_TO_RATE(pll_rate, div); in rk322x_mac_set_clk()
H A Dclk_px30.c1170 ulong pll_rate; in px30_mac_set_clk() local
1174 pll_rate = px30_clk_get_pll_rate(priv, CPLL); in px30_mac_set_clk()
1176 pll_rate = px30_clk_get_pll_rate(priv, NPLL); in px30_mac_set_clk()
1178 pll_rate = priv->gpll_hz; in px30_mac_set_clk()
1184 div = DIV_ROUND_UP(pll_rate, hz) - 1; in px30_mac_set_clk()
1189 return DIV_TO_RATE(pll_rate, div); in px30_mac_set_clk()
H A Dclk_rk3562.c1178 ulong pll_rate, now, best_rate = 0; in rk3562_vop_set_rate() local
1216 pll_rate = priv->gpll_hz; in rk3562_vop_set_rate()
1219 pll_rate = priv->hpll_hz; in rk3562_vop_set_rate()
1229 div = DIV_ROUND_UP(pll_rate, rate); in rk3562_vop_set_rate()
1232 now = pll_rate / div; in rk3562_vop_set_rate()
1239 pll_rate, best_rate, best_div, best_sel); in rk3562_vop_set_rate()
H A Dclk_rv1126.c1223 ulong pll_rate, now, best_rate = 0; in rv1126_dclk_vop_set_clk() local
1229 pll_rate = priv->gpll_hz; in rv1126_dclk_vop_set_clk()
1232 pll_rate = priv->cpll_hz; in rv1126_dclk_vop_set_clk()
1239 div = DIV_ROUND_UP(pll_rate, rate); in rv1126_dclk_vop_set_clk()
1242 now = pll_rate / div; in rv1126_dclk_vop_set_clk()
1249 pll_rate, best_rate, best_div, best_sel); in rv1126_dclk_vop_set_clk()
H A Dclk_rk3568.c1824 ulong pll_rate, now, best_rate = 0; in rk3568_dclk_vop_set_clk() local
1865 pll_rate = priv->gpll_hz; in rk3568_dclk_vop_set_clk()
1868 pll_rate = priv->cpll_hz; in rk3568_dclk_vop_set_clk()
1878 div = DIV_ROUND_UP(pll_rate, rate); in rk3568_dclk_vop_set_clk()
1881 now = pll_rate / div; in rk3568_dclk_vop_set_clk()
1888 pll_rate, best_rate, best_div, best_sel); in rk3568_dclk_vop_set_clk()
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_zynqmp.c424 ulong pll_rate, in zynqmp_clk_calc_peripheral_two_divs() argument
434 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynqmp_clk_calc_peripheral_two_divs()
455 ulong pll_rate, new_rate; in zynqmp_clk_set_peripheral_rate() local
468 pll_rate = zynqmp_clk_get_pll_rate(priv, pll); in zynqmp_clk_set_peripheral_rate()
469 if (IS_ERR_VALUE(pll_rate)) in zynqmp_clk_set_peripheral_rate()
470 return pll_rate; in zynqmp_clk_set_peripheral_rate()
475 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate, in zynqmp_clk_set_peripheral_rate()
479 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynqmp_clk_set_peripheral_rate()
H A Dclk_zynq.c289 ulong pll_rate, in zynq_clk_calc_peripheral_two_divs() argument
299 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynq_clk_calc_peripheral_two_divs()
320 ulong pll_rate, new_rate; in zynq_clk_set_peripheral_rate() local
327 pll_rate = zynq_clk_get_pll_rate(priv, pll); in zynq_clk_set_peripheral_rate()
331 new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate, in zynq_clk_set_peripheral_rate()
335 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynq_clk_set_peripheral_rate()