1176 	ulong pll_rate, now, best_rate = 0;  in rk3576_dclk_vop_set_clk()  local
1213 		pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],  in rk3576_dclk_vop_set_clk()
1215 		if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) {  in rk3576_dclk_vop_set_clk()
1216 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_vop_set_clk()
1238 				pll_rate = priv->gpll_hz;  in rk3576_dclk_vop_set_clk()
1241 				pll_rate = priv->cpll_hz;  in rk3576_dclk_vop_set_clk()
1244 				pll_rate = 0;  in rk3576_dclk_vop_set_clk()
1247 				pll_rate = 0;  in rk3576_dclk_vop_set_clk()
1250 				pll_rate = 0;  in rk3576_dclk_vop_set_clk()
1257 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_vop_set_clk()
1260 			now = pll_rate / div;  in rk3576_dclk_vop_set_clk()
1267 			      pll_rate, best_rate, best_div, best_sel);  in rk3576_dclk_vop_set_clk()
1318 	ulong pll_rate, now, best_rate = 0;  in rk3576_clk_csihost_set_clk()  local
1335 			pll_rate = priv->gpll_hz;  in rk3576_clk_csihost_set_clk()
1338 			pll_rate = priv->cpll_hz;  in rk3576_clk_csihost_set_clk()
1341 			pll_rate = 0;  in rk3576_clk_csihost_set_clk()
1344 			pll_rate = 0;  in rk3576_clk_csihost_set_clk()
1347 			pll_rate = 0;  in rk3576_clk_csihost_set_clk()
1350 			pll_rate = priv->spll_hz;  in rk3576_clk_csihost_set_clk()
1357 		div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_clk_csihost_set_clk()
1360 		now = pll_rate / div;  in rk3576_clk_csihost_set_clk()
1367 		      pll_rate, best_rate, best_div, best_sel);  in rk3576_clk_csihost_set_clk()
1436 	ulong pll_rate, now, best_rate = 0;  in rk3576_dclk_ebc_set_clk()  local
1445 			pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],  in rk3576_dclk_ebc_set_clk()
1447 			if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ &&  in rk3576_dclk_ebc_set_clk()
1448 			    pll_rate % rate == 0) {  in rk3576_dclk_ebc_set_clk()
1449 				div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_ebc_set_clk()
1478 					pll_rate = priv->gpll_hz;  in rk3576_dclk_ebc_set_clk()
1481 					pll_rate = priv->cpll_hz;  in rk3576_dclk_ebc_set_clk()
1484 					pll_rate = 0;  in rk3576_dclk_ebc_set_clk()
1487 					pll_rate = priv->aupll_hz;  in rk3576_dclk_ebc_set_clk()
1490 					pll_rate = 0;  in rk3576_dclk_ebc_set_clk()
1497 				div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_ebc_set_clk()
1500 				now = pll_rate / div;  in rk3576_dclk_ebc_set_clk()