| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | rk_spi.c | 54 uint input_rate; member
95 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk()
107 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
301 priv->input_rate = ret; in rockchip_spi_probe()
302 debug("%s: rate = %u\n", __func__, priv->input_rate); in rockchip_spi_probe()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 194 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) in clk_get_divisor() argument
198 clk_div = input_rate / output_rate; in clk_get_divisor()
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3066.c | 90 #define RATE_TO_DIV(input_rate, output_rate) \ argument
91 ((input_rate) / (output_rate) - 1);
93 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3036.c | 44 #define RATE_TO_DIV(input_rate, output_rate) \ argument
45 ((input_rate) / (output_rate) - 1);
47 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3328.c | 23 #define RATE_TO_DIV(input_rate, output_rate) \ argument
24 ((input_rate) / (output_rate) - 1);
25 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3188.c | 91 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3399.c | 44 #define RATE_TO_DIV(input_rate, output_rate) \ argument
45 ((input_rate) / (output_rate) - 1);
46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rv1108.c | 29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3128.c | 23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rv1103b.c | 23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk322x.c | 22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3308.c | 29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3506.c | 24 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3368.c | 62 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk1808.c | 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rv1106.c | 23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3288.c | 210 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3528.c | 21 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rv1126b.c | 22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_px30.c | 51 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3562.c | 20 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rv1126.c | 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| H A D | clk_rk3588.c | 22 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| /rk3399_rockchip-uboot/arch/arm/mach-exynos/ |
| H A D | clock.c | 1396 unsigned int fine_scalar_bits, unsigned int input_rate, in clock_calc_best_scalar() argument
1405 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate, in clock_calc_best_scalar()
1413 if (input_rate == 0 || target_rate == 0) in clock_calc_best_scalar()
1416 if (target_rate >= input_rate) in clock_calc_best_scalar()
1421 max(min(input_rate / i / target_rate, cap), 1U); in clock_calc_best_scalar()
1422 const unsigned int effective_rate = input_rate / i / in clock_calc_best_scalar()
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| /rk3399_rockchip-uboot/drivers/clk/aspeed/ |
| H A D | clk_ast2500.c | 179 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2500_calc_clock_config() argument
186 const ulong input_rate_khz = input_rate / 1000; in ast2500_calc_clock_config()
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