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Searched refs:hz (Results 1 – 25 of 58) sorted by relevance

123

/rk3399_rockchip-uboot/lib/
H A Dstrmhz.c9 char *strmhz (char *buf, unsigned long hz) in strmhz() argument
14 n = DIV_ROUND_CLOSEST(hz, 1000) / 1000L; in strmhz()
17 hz -= n * 1000000L; in strmhz()
18 m = DIV_ROUND_CLOSEST(hz, 1000L); in strmhz()
/rk3399_rockchip-uboot/drivers/spi/
H A Dcadence_qspi.c23 static int cadence_spi_write_speed(struct udevice *bus, uint hz) in cadence_spi_write_speed() argument
29 CONFIG_CQSPI_REF_CLK, hz); in cadence_spi_write_speed()
32 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, in cadence_spi_write_speed()
40 static int spi_calibration(struct udevice *bus, uint hz) in spi_calibration() argument
66 cadence_spi_write_speed(bus, hz); in spi_calibration()
113 priv->qspi_calibrated_hz = hz; in spi_calibration()
119 static int cadence_spi_set_speed(struct udevice *bus, uint hz) in cadence_spi_set_speed() argument
125 if (hz > plat->max_hz) in cadence_spi_set_speed()
126 hz = plat->max_hz; in cadence_spi_set_speed()
135 if (priv->previous_hz != hz || in cadence_spi_set_speed()
[all …]
H A Dmvebu_a3700_spi.c177 static int mvebu_spi_set_speed(struct udevice *bus, uint hz) in mvebu_spi_set_speed() argument
189 if (hz > plat->frequency) in mvebu_spi_set_speed()
190 hz = plat->frequency; in mvebu_spi_set_speed()
191 data |= plat->clock / hz; in mvebu_spi_set_speed()
/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Dclock_sun4i.c119 void clock_set_pll1(unsigned int hz) in clock_set_pll1() argument
127 while (pll1_para[i].freq > hz) in clock_set_pll1()
130 hz = pll1_para[i].freq; in clock_set_pll1()
131 if (! hz) in clock_set_pll1()
132 hz = 384000000; in clock_set_pll1()
135 axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ in clock_set_pll1()
136 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
139 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
228 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) in clock_set_de_mod_clock() argument
233 while ((pll / div) > hz) in clock_set_de_mod_clock()
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3308.c137 static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz) in rk3308_armclk_set_clk() argument
143 rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz); in rk3308_armclk_set_clk()
156 if (old_rate > hz) { in rk3308_armclk_set_clk()
158 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
167 } else if (old_rate < hz) { in rk3308_armclk_set_clk()
176 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
226 static ulong rk3308_i2c_set_clk(struct clk *clk, uint hz) in rk3308_i2c_set_clk() argument
232 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
260 static ulong rk3308_mac_set_clk(struct clk *clk, uint hz) in rk3308_mac_set_clk() argument
279 if (!hz) in rk3308_mac_set_clk()
[all …]
H A Dclk_rk1808.c134 ulong clk_id, uint hz) in rk1808_i2c_set_clk() argument
139 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_i2c_set_clk()
305 static ulong rk1808_saradc_set_clk(struct rk1808_clk_priv *priv, uint hz) in rk1808_saradc_set_clk() argument
310 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk1808_saradc_set_clk()
348 ulong clk_id, uint hz) in rk1808_pwm_set_clk() argument
353 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_pwm_set_clk()
394 static ulong rk1808_tsadc_set_clk(struct rk1808_clk_priv *priv, uint hz) in rk1808_tsadc_set_clk() argument
399 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk1808_tsadc_set_clk()
436 ulong clk_id, uint hz) in rk1808_spi_set_clk() argument
441 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_spi_set_clk()
[all …]
H A Dclk_px30.c327 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_i2c_set_clk() argument
332 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_i2c_set_clk()
453 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_i2s_set_clk() argument
460 rational_best_approximation(hz, clk_src, in px30_i2s_set_clk()
500 ulong hz) in px30_i2s1_mclk_set_clk() argument
504 if (hz == 12000000) { in px30_i2s1_mclk_set_clk()
508 px30_i2s_set_clk(priv, SCLK_I2S1, hz); in px30_i2s1_mclk_set_clk()
672 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) in px30_pwm_set_clk() argument
677 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pwm_set_clk()
714 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) in px30_saradc_set_clk() argument
[all …]
H A Dclk_rv1108.c31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
37 #hz "Hz cannot be hit with PLL "\
200 static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_saradc_set_clk() argument
204 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
225 static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio1_set_clk() argument
229 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio1_set_clk()
251 static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio0_set_clk() argument
[all …]
H A Dclk_rk3128.c91 static ulong rk3128_armclk_set_clk(struct rk3128_clk_priv *priv, ulong hz) in rk3128_armclk_set_clk() argument
97 rate = rockchip_get_cpu_settings(rk3128_cpu_rates, hz); in rk3128_armclk_set_clk()
110 if (old_rate > hz) { in rk3128_armclk_set_clk()
112 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
122 } else if (old_rate < hz) { in rk3128_armclk_set_clk()
132 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
259 ulong clk_id, uint hz) in rk3128_peri_set_clk() argument
266 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_peri_set_clk()
281 hz); in rk3128_peri_set_clk()
290 hz); in rk3128_peri_set_clk()
[all …]
H A Dclk_rk3328.c118 static ulong rk3328_armclk_set_clk(struct rk3328_clk_priv *priv, ulong hz) in rk3328_armclk_set_clk() argument
124 rate = rockchip_get_cpu_settings(rk3328_cpu_rates, hz); in rk3328_armclk_set_clk()
137 if (old_rate > hz) { in rk3328_armclk_set_clk()
139 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
149 } else if (old_rate < hz) { in rk3328_armclk_set_clk()
159 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
198 ulong clk_id, uint hz) in rk3328_i2c_set_clk() argument
203 src_clk_div = priv->gpll_hz / hz; in rk3328_i2c_set_clk()
400 static ulong rk3328_spi_set_clk(struct rk3328_clk_priv *priv, uint hz) in rk3328_spi_set_clk() argument
403 u32 div = priv->gpll_hz / hz; in rk3328_spi_set_clk()
[all …]
H A Dclk_rk3368.c106 #define PLL_DIVISORS(hz, _nr, _no) { \ argument
107 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
108 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
109 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
536 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) in rk3368_spi_set_clk() argument
541 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); in rk3368_spi_set_clk()
574 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) in rk3368_saradc_set_clk() argument
578 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3368_saradc_set_clk()
620 ulong clk_id, ulong hz) in rk3368_bus_set_clk() argument
630 src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz); in rk3368_bus_set_clk()
[all …]
H A Dclk_rk322x.c92 static ulong rk322x_armclk_set_clk(struct rk322x_clk_priv *priv, ulong hz) in rk322x_armclk_set_clk() argument
98 rate = rockchip_get_cpu_settings(rk322x_cpu_rates, hz); in rk322x_armclk_set_clk()
111 if (old_rate > hz) { in rk322x_armclk_set_clk()
113 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
123 } else if (old_rate < hz) { in rk322x_armclk_set_clk()
133 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
304 ulong clk_id, ulong hz) in rk322x_bus_set_clk() argument
315 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_bus_set_clk()
325 hz); in rk322x_bus_set_clk()
334 hz); in rk322x_bus_set_clk()
[all …]
H A Dclk_rk3188.c93 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
94 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
95 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
96 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
140 unsigned int hz, bool has_bwadj) in rkclk_configure_ddr() argument
150 switch (hz) { in rkclk_configure_ddr()
186 unsigned int hz, bool has_bwadj) in rkclk_configure_cpu() argument
201 switch (hz) { in rkclk_configure_cpu()
241 return hz; in rkclk_configure_cpu()
401 static ulong rk3188_saradc_set_clk(struct rk3188_cru *cru, uint hz) in rk3188_saradc_set_clk() argument
[all …]
H A Dclk_rk3066.c95 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
96 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
97 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
98 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
142 unsigned int hz, bool has_bwadj) in rkclk_configure_ddr() argument
152 switch (hz) { in rkclk_configure_ddr()
188 unsigned int hz, bool has_bwadj) in rkclk_configure_cpu() argument
203 switch (hz) { in rkclk_configure_cpu()
243 return hz; in rkclk_configure_cpu()
H A Dclk_rk3036.c49 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
53 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
54 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
55 #hz "Hz cannot be hit with PLL "\
348 ulong hz) in rk3036_spi_set_clk() argument
352 div = DIV_ROUND_UP(clk_general_rate, hz); in rk3036_spi_set_clk()
452 uint hz) in rk3036_peri_set_clk() argument
459 src_clk_div = DIV_ROUND_UP(clk_general_rate, hz); in rk3036_peri_set_clk()
470 hz); in rk3036_peri_set_clk()
H A Dclk_rk3399.c48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};
621 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) in rk3399_i2c_set_clk() argument
626 src_clk_div = GPLL_HZ / hz; in rk3399_i2c_set_clk()
720 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) in rk3399_spi_set_clk() argument
725 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rk3399_spi_set_clk()
749 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) in rk3399_vop_set_clk() argument
782 if (pll_para_config(hz, &cpll_config)) in rk3399_vop_set_clk()
786 if (pll_para_config(hz, &vpll_config)) in rk3399_vop_set_clk()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Duniphier-ld20.dtsi84 opp-hz = /bits/ 64 <250000000>;
88 opp-hz = /bits/ 64 <275000000>;
92 opp-hz = /bits/ 64 <500000000>;
96 opp-hz = /bits/ 64 <550000000>;
100 opp-hz = /bits/ 64 <666667000>;
104 opp-hz = /bits/ 64 <733334000>;
108 opp-hz = /bits/ 64 <1000000000>;
112 opp-hz = /bits/ 64 <1100000000>;
122 opp-hz = /bits/ 64 <250000000>;
126 opp-hz = /bits/ 64 <275000000>;
[all …]
H A Duniphier-pro5.dtsi45 opp-hz = /bits/ 64 <100000000>;
49 opp-hz = /bits/ 64 <116667000>;
53 opp-hz = /bits/ 64 <150000000>;
57 opp-hz = /bits/ 64 <175000000>;
61 opp-hz = /bits/ 64 <200000000>;
65 opp-hz = /bits/ 64 <233334000>;
69 opp-hz = /bits/ 64 <300000000>;
73 opp-hz = /bits/ 64 <350000000>;
77 opp-hz = /bits/ 64 <400000000>;
81 opp-hz = /bits/ 64 <466667000>;
[all …]
H A Duniphier-ld11.dtsi57 opp-hz = /bits/ 64 <245000000>;
61 opp-hz = /bits/ 64 <250000000>;
65 opp-hz = /bits/ 64 <490000000>;
69 opp-hz = /bits/ 64 <500000000>;
73 opp-hz = /bits/ 64 <653334000>;
77 opp-hz = /bits/ 64 <666667000>;
81 opp-hz = /bits/ 64 <980000000>;
H A Duniphier-pxs3.dtsi81 opp-hz = /bits/ 64 <250000000>;
85 opp-hz = /bits/ 64 <325000000>;
89 opp-hz = /bits/ 64 <500000000>;
93 opp-hz = /bits/ 64 <650000000>;
97 opp-hz = /bits/ 64 <666667000>;
101 opp-hz = /bits/ 64 <866667000>;
105 opp-hz = /bits/ 64 <1000000000>;
109 opp-hz = /bits/ 64 <1300000000>;
H A Duniphier-pxs2.dtsi65 opp-hz = /bits/ 64 <100000000>;
69 opp-hz = /bits/ 64 <150000000>;
73 opp-hz = /bits/ 64 <200000000>;
77 opp-hz = /bits/ 64 <300000000>;
81 opp-hz = /bits/ 64 <400000000>;
85 opp-hz = /bits/ 64 <600000000>;
89 opp-hz = /bits/ 64 <800000000>;
93 opp-hz = /bits/ 64 <1200000000>;
/rk3399_rockchip-uboot/drivers/mmc/
H A Dsunxi_mmc.c96 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) in mmc_set_mod_clk() argument
110 hz = hz * 2; in mmc_set_mod_clk()
112 if (hz <= 24000000) { in mmc_set_mod_clk()
125 div = pll_hz / hz; in mmc_set_mod_clk()
126 if (pll_hz % hz) in mmc_set_mod_clk()
137 hz); in mmc_set_mod_clk()
142 if (hz <= 400000) { in mmc_set_mod_clk()
145 } else if (hz <= 25000000) { in mmc_set_mod_clk()
149 } else if (hz <= 50000000) { in mmc_set_mod_clk()
157 } else if (hz <= 50000000) { in mmc_set_mod_clk()
[all …]
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_pic32.c118 ulong hz; in pic32_get_sysclk() local
130 hz = SYS_FRC_CLK_HZ / div; in pic32_get_sysclk()
134 hz = pic32_get_pll_rate(priv); in pic32_get_sysclk()
138 hz = SYS_POSC_CLK_HZ; in pic32_get_sysclk()
142 hz = 0; in pic32_get_sysclk()
147 return hz; in pic32_get_sysclk()
/rk3399_rockchip-uboot/drivers/power/dvfs/
H A Drockchip_wtemp_dvfs.c82 u64 hz; member
154 if (opp[i].hz >= rate) { in wtemp_get_lowlevel_rate()
160 return opp[idx].hz; in wtemp_get_lowlevel_rate()
249 tgt_rate = e->opp[0].hz; in wtemp_dvfs_high_temp_adjust()
320 uint64_t hz; in __wtemp_common_ofdata_to_platdata() local
364 ofnode_read_u64(node, "opp-hz", &hz); in __wtemp_common_ofdata_to_platdata()
366 e->opp[e->opp_nr].hz = hz; in __wtemp_common_ofdata_to_platdata()
371 hz, uv, ofnode_get_name(node)); in __wtemp_common_ofdata_to_platdata()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Dclock.h32 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);

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