327 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)  in px30_i2c_set_clk()  argument
332 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_i2c_set_clk()
453 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)  in px30_i2s_set_clk()  argument
460 	rational_best_approximation(hz, clk_src,  in px30_i2s_set_clk()
500 				    ulong hz)  in px30_i2s1_mclk_set_clk()  argument
504 	if (hz == 12000000) {  in px30_i2s1_mclk_set_clk()
508 		px30_i2s_set_clk(priv, SCLK_I2S1, hz);  in px30_i2s1_mclk_set_clk()
672 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)  in px30_pwm_set_clk()  argument
677 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_pwm_set_clk()
714 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz)  in px30_saradc_set_clk()  argument
719 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);  in px30_saradc_set_clk()
740 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz)  in px30_tsadc_set_clk()  argument
745 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);  in px30_tsadc_set_clk()
777 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)  in px30_spi_set_clk()  argument
782 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_spi_set_clk()
837 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz)  in px30_vop_set_clk()  argument
846 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_vop_set_clk()
854 		if (hz < PX30_VOP_PLL_LIMIT) {  in px30_vop_set_clk()
855 			src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz);  in px30_vop_set_clk()
862 		rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div);  in px30_vop_set_clk()
872 		if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz && npll_hz % hz == 0) {  in px30_vop_set_clk()
873 			src_clk_div = npll_hz / hz;  in px30_vop_set_clk()
876 			if (hz < PX30_VOP_PLL_LIMIT) {  in px30_vop_set_clk()
877 				src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz);  in px30_vop_set_clk()
884 			rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div);  in px30_vop_set_clk()
931 			      ulong hz)  in px30_bus_set_clk()  argument
942 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_bus_set_clk()
950 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_bus_set_clk()
959 			DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz);  in px30_bus_set_clk()
997 			       ulong hz)  in px30_peri_set_clk()  argument
1002 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_peri_set_clk()
1065 			      ulong hz)  in px30_otp_set_clk()  argument
1071 		if ((OSC_HZ % hz) == 0) {  in px30_otp_set_clk()
1078 		div = DIV_ROUND_UP(parent, hz);  in px30_otp_set_clk()
1088 		div = DIV_ROUND_UP(OSC_HZ, hz);  in px30_otp_set_clk()
1094 		div = DIV_ROUND_UP(px30_otp_get_clk(priv, SCLK_OTP), hz);  in px30_otp_set_clk()
1131 				 ulong hz)  in px30_crypto_set_clk()  argument
1136 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_crypto_set_clk()
1165 static ulong px30_mac_set_clk(struct clk *clk, uint hz)  in px30_mac_set_clk()  argument
1181 	if (!hz)  in px30_mac_set_clk()
1182 		hz = 50000000;  in px30_mac_set_clk()
1184 	div = DIV_ROUND_UP(pll_rate, hz) - 1;  in px30_mac_set_clk()
1192 static int px30_mac_set_speed_clk(struct clk *clk, uint hz)  in px30_mac_set_speed_clk()  argument
1197 	if (hz != 2500000 && hz != 25000000) {  in px30_mac_set_speed_clk()
1198 		debug("Unsupported mac speed:%d\n", hz);  in px30_mac_set_speed_clk()
1203 		     ((hz == 2500000) ? 0 : 1) << RMII_CLK_SEL_SHIFT);  in px30_mac_set_speed_clk()
1238 				   enum px30_pll_id pll_id, ulong hz)  in px30_clk_set_pll_rate()  argument
1242 	if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz))  in px30_clk_set_pll_rate()
1247 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz)  in px30_armclk_set_clk()  argument
1253 	rate = get_cpu_settings(hz);  in px30_armclk_set_clk()
1265 	if (old_rate > hz) {  in px30_armclk_set_clk()
1266 		if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz))  in px30_armclk_set_clk()
1275 	} else if (old_rate < hz) {  in px30_armclk_set_clk()
1283 		if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz))  in px30_armclk_set_clk()
1747 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)  in px30_pclk_pmu_set_pmuclk()  argument
1752 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_pclk_pmu_set_pmuclk()
1769 static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz)  in px30_gpll_set_pmuclk()  argument
1789 	if (priv->gpll_hz == hz)  in px30_gpll_set_pmuclk()
1793 	div = DIV_ROUND_UP(hz, priv->gpll_hz);  in px30_gpll_set_pmuclk()
1827 	rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz);  in px30_gpll_set_pmuclk()