48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\  argument
50 	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
51 	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};
621 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)  in rk3399_i2c_set_clk()  argument
626 	src_clk_div = GPLL_HZ / hz;  in rk3399_i2c_set_clk()
720 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)  in rk3399_spi_set_clk()  argument
725 	src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;  in rk3399_spi_set_clk()
749 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)  in rk3399_vop_set_clk()  argument
782 		if (pll_para_config(hz, &cpll_config))  in rk3399_vop_set_clk()
786 		if (pll_para_config(hz, &vpll_config))  in rk3399_vop_set_clk()
796 	return hz;  in rk3399_vop_set_clk()
969 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)  in rk3399_saradc_set_clk()  argument
973 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;  in rk3399_saradc_set_clk()
994 static ulong rk3399_tsadc_set_clk(struct rk3399_cru *cru, uint hz)  in rk3399_tsadc_set_clk()  argument
998 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;  in rk3399_tsadc_set_clk()
1033 				   ulong hz)  in rk3399_crypto_set_clk()  argument
1038 	src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);  in rk3399_crypto_set_clk()
1625 				   uint hz)  in rk3399_i2c_set_pmuclk()  argument
1629 	src_clk_div = PPLL_HZ / hz;  in rk3399_i2c_set_pmuclk()