118 static ulong rk3328_armclk_set_clk(struct rk3328_clk_priv *priv, ulong hz)  in rk3328_armclk_set_clk()  argument
124 	rate = rockchip_get_cpu_settings(rk3328_cpu_rates, hz);  in rk3328_armclk_set_clk()
137 	if (old_rate > hz) {  in rk3328_armclk_set_clk()
139 					  priv->cru, NPLL, hz))  in rk3328_armclk_set_clk()
149 	} else if (old_rate < hz) {  in rk3328_armclk_set_clk()
159 					  priv->cru, NPLL, hz))  in rk3328_armclk_set_clk()
198 				ulong clk_id, uint hz)  in rk3328_i2c_set_clk()  argument
203 	src_clk_div = priv->gpll_hz / hz;  in rk3328_i2c_set_clk()
400 static ulong rk3328_spi_set_clk(struct rk3328_clk_priv *priv, uint hz)  in rk3328_spi_set_clk()  argument
403 	u32 div = priv->gpll_hz / hz;  in rk3328_spi_set_clk()
425 static ulong rk3328_pwm_set_clk(struct rk3328_clk_priv *priv, uint hz)  in rk3328_pwm_set_clk()  argument
428 	u32 div = priv->gpll_hz / hz;  in rk3328_pwm_set_clk()
450 static ulong rk3328_saradc_set_clk(struct rk3328_clk_priv *priv, uint hz)  in rk3328_saradc_set_clk()  argument
455 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;  in rk3328_saradc_set_clk()
477 static ulong rk3328_tsadc_set_clk(struct rk3328_clk_priv *priv, uint hz)  in rk3328_tsadc_set_clk()  argument
482 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;  in rk3328_tsadc_set_clk()
524 				ulong clk_id, uint hz)  in rk3328_vop_set_clk()  argument
530 	src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz);  in rk3328_vop_set_clk()
552 					   hz);  in rk3328_vop_set_clk()
565 				src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz);  in rk3328_vop_set_clk()
567 				src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk3328_vop_set_clk()
613 				ulong clk_id, ulong hz)  in rk3328_bus_set_clk()  argument
624 		src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz);  in rk3328_bus_set_clk()
636 					   hz);  in rk3328_bus_set_clk()
645 					   hz);  in rk3328_bus_set_clk()
687 				 ulong clk_id, ulong hz)  in rk3328_peri_set_clk()  argument
698 		src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz);  in rk3328_peri_set_clk()
710 					   hz);  in rk3328_peri_set_clk()
719 					   hz);  in rk3328_peri_set_clk()
753 				   ulong hz)  in rk3328_crypto_set_clk()  argument
758 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk3328_crypto_set_clk()