106 #define PLL_DIVISORS(hz, _nr, _no) { \  argument
107 	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
108 	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
109 		       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
536 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)  in rk3368_spi_set_clk()  argument
541 	src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);  in rk3368_spi_set_clk()
574 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)  in rk3368_saradc_set_clk()  argument
578 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;  in rk3368_saradc_set_clk()
620 				ulong clk_id, ulong hz)  in rk3368_bus_set_clk()  argument
630 		src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz);  in rk3368_bus_set_clk()
640 					   hz);  in rk3368_bus_set_clk()
649 					   hz);  in rk3368_bus_set_clk()
694 				 ulong clk_id, ulong hz)  in rk3368_peri_set_clk()  argument
704 		src_clk_div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, GPLL), hz);  in rk3368_peri_set_clk()
714 					   hz);  in rk3368_peri_set_clk()
723 					   hz);  in rk3368_peri_set_clk()
768 static ulong rk3368_vop_set_clk(struct rk3368_cru *cru, int clk_id, uint hz)  in rk3368_vop_set_clk()  argument
776 		if (!(NPLL_HZ % hz)) {  in rk3368_vop_set_clk()
778 			lcdc_div = NPLL_HZ / hz;  in rk3368_vop_set_clk()
780 			ret = pll_para_config(hz, &npll_config, &lcdc_div);  in rk3368_vop_set_clk()
794 		if ((rkclk_pll_get_rate(cru, CPLL) % hz) == 0) {  in rk3368_vop_set_clk()
795 			lcdc_div = rkclk_pll_get_rate(cru, CPLL) / hz;  in rk3368_vop_set_clk()
806 			lcdc_div = rkclk_pll_get_rate(cru, GPLL) / hz;  in rk3368_vop_set_clk()
849 				    uint hz)  in rk3368_crypto_set_rate()  argument
856 	src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1;  in rk3368_crypto_set_rate()
868 				   int clk_id, ulong hz)  in rk3368_armclk_set_clk()  argument
877 	rate = rockchip_get_cpu_settings(rk3368_cpu_rates, hz);  in rk3368_armclk_set_clk()
889 	ret = pll_para_config(hz, &pll_config, &pll_div);  in rk3368_armclk_set_clk()
903 	if (old_rate > hz) {  in rk3368_armclk_set_clk()
913 	} else if (old_rate < hz) {  in rk3368_armclk_set_clk()