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Searched refs:pll (Results 1 – 25 of 28) sorted by relevance

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/rk3399_ARM-atf/fdts/
H A Dstm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi57 pll1: st,pll-1 {
58 st,pll = <&pll1_cfg_1200Mhz>;
66 pll2: st,pll-2 {
67 st,pll = <&pll2_cfg_600Mhz>;
75 pll4: st,pll-4 {
76 st,pll = <&pll4_cfg_1200Mhz>;
84 pll5: st,pll-5 {
85 st,pll = <&pll5_cfg_532Mhz>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi60 pll1: st,pll-1 {
61 st,pll = <&pll1_cfg_1200Mhz>;
69 pll2: st,pll-2 {
70 st,pll = <&pll2_cfg_600Mhz>;
78 pll4: st,pll-4 {
79 st,pll = <&pll4_cfg_1200Mhz>;
87 pll5: st,pll-5 {
88 st,pll = <&pll5_cfg_532Mhz>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi62 pll1: st,pll-1 {
63 st,pll = <&pll1_cfg_1200Mhz>;
71 pll2: st,pll-2 {
72 st,pll = <&pll2_cfg_600Mhz>;
80 pll4: st,pll-4 {
81 st,pll = <&pll4_cfg_1200Mhz>;
89 pll5: st,pll-5 {
90 st,pll = <&pll5_cfg_532Mhz>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi62 pll1: st,pll-1 {
63 st,pll = <&pll1_cfg_1200Mhz>;
71 pll2: st,pll-2 {
72 st,pll = <&pll2_cfg_600Mhz>;
80 pll4: st,pll-4 {
81 st,pll = <&pll4_cfg_1200Mhz>;
89 pll5: st,pll-5 {
90 st,pll = <&pll5_cfg_532Mhz>;
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi62 pll1: st,pll-1 {
63 st,pll = <&pll1_cfg_1200MHz>;
71 pll2: st,pll-2 {
72 st,pll = <&pll2_cfg_400MHz>;
80 pll4: st,pll-4 {
81 st,pll = <&pll4_cfg_1200MHz>;
H A Dstm32mp151a-prtt1a.dts148 pll2: st,pll@1 {
149 compatible = "st,stm32mp1-pll";
152 st,pll = <&pll2_cfg1>;
161 pll3: st,pll@2 {
162 compatible = "st,stm32mp1-pll";
165 st,pll = <&pll3_cfg1>;
174 pll4: st,pll@3 {
175 compatible = "st,stm32mp1-pll";
178 st,pll = <&pll4_cfg1>;
H A Dstm32mp15xx-osd32.dtsi268 pll2: st,pll@1 {
269 compatible = "st,stm32mp1-pll";
272 st,pll = <&pll2_cfg1>;
281 pll3: st,pll@2 {
282 compatible = "st,stm32mp1-pll";
285 st,pll = <&pll3_cfg1>;
294 pll4: st,pll@3 {
295 compatible = "st,stm32mp1-pll";
298 st,pll = <&pll4_cfg1>;
H A Dstm32mp15xx-dkx.dtsi247 pll2: st,pll@1 {
248 compatible = "st,stm32mp1-pll";
251 st,pll = <&pll2_cfg1>;
260 pll3: st,pll@2 {
261 compatible = "st,stm32mp1-pll";
264 st,pll = <&pll3_cfg1>;
273 pll4: st,pll@3 {
274 compatible = "st,stm32mp1-pll";
277 st,pll = <&pll4_cfg1>;
H A Dstm32mp135f-dk.dts239 pll2:st,pll@1 {
240 compatible = "st,stm32mp1-pll";
243 st,pll = <&pll2_cfg1>;
252 pll3:st,pll@2 {
253 compatible = "st,stm32mp1-pll";
256 st,pll = <&pll3_cfg1>;
265 pll4:st,pll@3 {
266 compatible = "st,stm32mp1-pll";
269 st,pll = <&pll4_cfg1>;
H A Dstm32mp15xx-dhcor-som.dtsi271 pll2: st,pll@1 {
272 compatible = "st,stm32mp1-pll";
275 st,pll = <&pll2_cfg1>;
284 pll3: st,pll@2 {
285 compatible = "st,stm32mp1-pll";
288 st,pll = <&pll3_cfg1>;
298 pll4: st,pll@3 {
299 compatible = "st,stm32mp1-pll";
302 st,pll = <&pll4_cfg1>;
H A Dstm32mp157c-ed1.dts245 pll2: st,pll@1 {
246 compatible = "st,stm32mp1-pll";
249 st,pll = <&pll2_cfg1>;
258 pll3: st,pll@2 {
259 compatible = "st,stm32mp1-pll";
262 st,pll = <&pll3_cfg1>;
271 pll4: st,pll@3 {
272 compatible = "st,stm32mp1-pll";
275 st,pll = <&pll4_cfg1>;
H A Dstm32mp157c-odyssey-som.dtsi290 pll2: st,pll@1 {
291 compatible = "st,stm32mp1-pll";
294 st,pll = <&pll2_cfg1>;
303 pll3: st,pll@2 {
304 compatible = "st,stm32mp1-pll";
307 st,pll = <&pll3_cfg1>;
316 pll4: st,pll@3 {
317 compatible = "st,stm32mp1-pll";
320 st,pll = <&pll4_cfg1>;
H A Dstm32mp157a-avenger96.dts259 pll2: st,pll@1 {
260 compatible = "st,stm32mp1-pll";
263 st,pll = <&pll2_cfg1>;
272 pll3: st,pll@2 {
273 compatible = "st,stm32mp1-pll";
276 st,pll = <&pll3_cfg1>;
285 pll4: st,pll@3 {
286 compatible = "st,stm32mp1-pll";
289 st,pll = <&pll4_cfg1>;
H A Dstm32mp15xx-dhcom-som.dtsi276 pll2: st,pll@1 {
277 compatible = "st,stm32mp1-pll";
280 st,pll = <&pll2_cfg1>;
289 pll3: st,pll@2 {
290 compatible = "st,stm32mp1-pll";
293 st,pll = <&pll3_cfg1>;
302 pll4: st,pll@3 {
303 compatible = "st,stm32mp1-pll";
306 st,pll = <&pll4_cfg1>;
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp2.c48 struct stm32_pll_dt_cfg *pll; member
976 const struct stm32_clk_pll *pll, in clk_get_pll_fvco() argument
981 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; in clk_get_pll_fvco()
1010 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) in _clk_stm32_pll_is_enabled() argument
1012 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; in _clk_stm32_pll_is_enabled()
1017 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) in _clk_stm32_pll_set_on() argument
1019 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; in _clk_stm32_pll_set_on()
1024 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) in _clk_stm32_pll_set_off() argument
1026 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; in _clk_stm32_pll_set_off()
1033 const struct stm32_clk_pll *pll) in _clk_stm32_pll_wait_ready_on() argument
[all …]
H A Dstm32mp1_clk.c62 struct stm32_pll_dt_cfg *pll; member
1032 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) in stm32mp1_pll_get_fref() argument
1034 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); in stm32mp1_pll_get_fref()
1037 return stm32mp1_clk_get_fixed(pll->refclk[src]); in stm32mp1_pll_get_fref()
1046 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) in stm32mp1_pll_get_fvco() argument
1052 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); in stm32mp1_pll_get_fvco()
1053 fracr = mmio_read_32(rcc_base + pll->pllxfracr); in stm32mp1_pll_get_fvco()
1058 refclk = stm32mp1_pll_get_fref(pll); in stm32mp1_pll_get_fvco()
1085 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_read_pll_freq() local
1093 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); in stm32mp1_read_pll_freq()
[all …]
H A Dclk-stm32mp13.c82 struct stm32_pll_dt_cfg *pll; member
1311 const struct stm32_clk_pll *pll, in clk_stm32_pll_compute_cfgr1() argument
1320 prate = _clk_stm32_get_parent_rate(priv, pll->clk_id); in clk_stm32_pll_compute_cfgr1()
1323 if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) || in clk_stm32_pll_compute_cfgr1()
1324 (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) { in clk_stm32_pll_compute_cfgr1()
1330 if ((pll->plltype == PLL_800) && (refclk >= 8000000U)) { in clk_stm32_pll_compute_cfgr1()
1352 const struct stm32_clk_pll *pll, in clk_stm32_pll_config_vco() argument
1355 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in clk_stm32_pll_config_vco()
1358 if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) { in clk_stm32_pll_config_vco()
1375 const struct stm32_clk_pll *pll, in clk_stm32_pll_config_csg() argument
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/
H A Dgpc_common.c262 struct pll_override pll[MAX_PLL_NUM] = { variable
286 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); in imx_anamix_override()
287 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); in imx_anamix_override()
289 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); in imx_anamix_override()
290 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); in imx_anamix_override()
/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk_drv.c200 const struct s32cc_pll *pll = s32cc_obj2pll(module); in get_pll_parent() local
202 if (pll->source == NULL) { in get_pll_parent()
206 return pll->source; in get_pll_parent()
246 static struct s32cc_clkmux *get_pll_mux(const struct s32cc_pll *pll) in get_pll_mux() argument
248 const struct s32cc_clk_obj *source = pll->source; in get_pll_mux()
300 static int adjust_odiv_settings(const struct s32cc_pll *pll, uintptr_t pll_addr, in adjust_odiv_settings() argument
311 for (i = 0; i < pll->ndividers; i++) { in adjust_odiv_settings()
321 pdiv = (uint32_t)(pll->vco_freq * FP_PRECISION / old_odiv_freq / FP_PRECISION); in adjust_odiv_settings()
323 odiv_freq = pll->vco_freq * FP_PRECISION / pdiv / FP_PRECISION; in adjust_odiv_settings()
396 static int program_pll(const struct s32cc_pll *pll, uintptr_t pll_addr, in program_pll() argument
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.c107 uint32_t *pll = slp_data.pll_con[pll_id]; in pll_save() local
109 pll[0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in pll_save()
110 pll[1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in pll_save()
111 pll[2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in pll_save()
112 pll[3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in pll_save()
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.c2802 struct pm_pll *pll = NULL; in pm_clock_get_pll() local
2806 pll = &pm_plls[i]; in pm_clock_get_pll()
2811 return pll; in pm_clock_get_pll()
2825 const struct pm_pll *pll = pm_clock_get_pll(clock_id); in pm_clock_get_pll_node_id() local
2828 if (pll != NULL) { in pm_clock_get_pll_node_id()
2829 *node_id = pll->nid; in pm_clock_get_pll_node_id()
2847 struct pm_pll *pll = NULL; in pm_clock_get_pll_by_related_clk() local
2854 pll = &pm_plls[i]; in pm_clock_get_pll_by_related_clk()
2859 return pll; in pm_clock_get_pll_by_related_clk()
2874 enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll, uint32_t flag) in pm_clock_pll_enable() argument
[all …]
H A Dpm_api_clock.h319 enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll, uint32_t flag);
320 enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll, uint32_t flag);
321 enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
324 enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll,
328 enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll,
H A Dzynqmp_pm_api_sys.c1224 struct pm_pll *pll; in pm_clock_enable() local
1228 pll = pm_clock_get_pll(clock_id); in pm_clock_enable()
1229 if (pll != NULL) { in pm_clock_enable()
1230 ret = pm_clock_pll_enable(pll, flag); in pm_clock_enable()
1255 struct pm_pll *pll; in pm_clock_disable() local
1259 pll = pm_clock_get_pll(clock_id); in pm_clock_disable()
1260 if (pll != NULL) { in pm_clock_disable()
1261 ret = pm_clock_pll_disable(pll, flag); in pm_clock_disable()
1288 struct pm_pll *pll; in pm_clock_getstate() local
1293 pll = pm_clock_get_pll(clock_id); in pm_clock_getstate()
[all …]
H A Dpm_api_ioctl.c362 (uint32_t pll, uint32_t mode) in pm_ioctl_set_pll_frac_mode() argument
364 return pm_clock_set_pll_mode(pll, mode); in pm_ioctl_set_pll_frac_mode()
378 (uint32_t pll, uint32_t *mode) in pm_ioctl_get_pll_frac_mode() argument
380 return pm_clock_get_pll_mode(pll, mode); in pm_ioctl_get_pll_frac_mode()
397 (uint32_t pll, uint32_t data, uint32_t flag) in pm_ioctl_set_pll_frac_data() argument
403 status = pm_clock_get_pll_node_id(pll, &pll_nid); in pm_ioctl_set_pll_frac_data()
425 (uint32_t pll, uint32_t *data, uint32_t flag) in pm_ioctl_get_pll_frac_data() argument
431 status = pm_clock_get_pll_node_id(pll, &pll_nid); in pm_ioctl_get_pll_frac_data()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupwr_clkctl.h16 int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain);

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