1*296b5902SFlora Fu /* 2*296b5902SFlora Fu * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*296b5902SFlora Fu * 4*296b5902SFlora Fu * SPDX-License-Identifier: BSD-3-Clause 5*296b5902SFlora Fu */ 6*296b5902SFlora Fu 7*296b5902SFlora Fu #ifndef APUPWR_CLKCTL_H 8*296b5902SFlora Fu #define APUPWR_CLKCTL_H 9*296b5902SFlora Fu 10*296b5902SFlora Fu #include <arch_helpers.h> 11*296b5902SFlora Fu #include <apupwr_clkctl_def.h> 12*296b5902SFlora Fu 13*296b5902SFlora Fu int32_t apupwr_smc_acc_init_all(void); 14*296b5902SFlora Fu void apupwr_smc_acc_top(bool enable); 15*296b5902SFlora Fu int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain); 16*296b5902SFlora Fu int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain); 17*296b5902SFlora Fu int32_t apupwr_smc_bulk_pll(bool enable); 18*296b5902SFlora Fu void apupwr_smc_bus_prot_cg_on(void); 19*296b5902SFlora Fu 20*296b5902SFlora Fu int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en); 21*296b5902SFlora Fu int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain, 22*296b5902SFlora Fu enum pll_set_rate_mode mode, int32_t freq); 23*296b5902SFlora Fu #endif /* APUPWR_CLKCTL_H */ 24