48 	struct stm32_pll_dt_cfg *pll;  member
736 				      const struct stm32_clk_pll *pll,  in clk_get_pll_fvco()  argument
741 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_get_pll_fvco()
770 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_is_enabled()  argument
772 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_is_enabled()
777 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_set_on()  argument
779 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_set_on()
784 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_set_off()  argument
786 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_set_off()
793 					const struct stm32_clk_pll *pll)  in _clk_stm32_pll_wait_ready_on()  argument
795 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_wait_ready_on()
802 			      pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcfgr1,  in _clk_stm32_pll_wait_ready_on()
812 					 const struct stm32_clk_pll *pll)  in _clk_stm32_pll_wait_ready_off()  argument
814 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_wait_ready_off()
821 			      pll->clk_id - _CK_PLL1 + 1, pllxcfgr1, mmio_read_32(pllxcfgr1));  in _clk_stm32_pll_wait_ready_off()
829 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_enable()  argument
831 	if (_clk_stm32_pll_is_enabled(priv, pll)) {  in _clk_stm32_pll_enable()
835 	_clk_stm32_pll_set_on(priv, pll);  in _clk_stm32_pll_enable()
837 	return _clk_stm32_pll_wait_ready_on(priv, pll);  in _clk_stm32_pll_enable()
840 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_disable()  argument
842 	if (!_clk_stm32_pll_is_enabled(priv, pll)) {  in _clk_stm32_pll_disable()
846 	_clk_stm32_pll_set_off(priv, pll);  in _clk_stm32_pll_disable()
848 	_clk_stm32_pll_wait_ready_off(priv, pll);  in _clk_stm32_pll_disable()
855 	const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);  in clk_stm32_pll_is_enabled()  local
857 	return _clk_stm32_pll_is_enabled(priv, pll);  in clk_stm32_pll_is_enabled()
864 	const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);  in clk_stm32_pll_enable()  local
866 	return _clk_stm32_pll_enable(priv, pll);  in clk_stm32_pll_enable()
873 	const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);  in clk_stm32_pll_disable()  local
875 	_clk_stm32_pll_disable(priv, pll);  in clk_stm32_pll_disable()
883 	const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);  in clk_stm32_pll_recalc_rate()  local
884 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_recalc_rate()
900 			dfout = clk_get_pll_fvco(priv, pll, prate) / (postdiv1 * postdiv2);  in clk_stm32_pll_recalc_rate()
1625 				       const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_output()  argument
1629 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_output()
1637 	refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id);  in clk_stm32_pll_config_output()
1697 				     const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_csg()  argument
1700 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_csg()
1734 	return  &pdata->pll[pll_idx];  in clk_stm32_pll_get_pdata()
1740 	const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);  in _clk_stm32_pll1_init()  local
1751 	refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id);  in _clk_stm32_pll1_init()
1774 					const struct stm32_clk_pll *pll)  in clk_stm32_pll_wait_mux_ready()  argument
1776 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_wait_mux_ready()
1782 			EARLY_ERROR("PLL%d ref clock not started\n", pll->clk_id - _CK_PLL1 + 1);  in clk_stm32_pll_wait_mux_ready()
1793 	const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);  in _clk_stm32_pll_init()  local
1794 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_init()
1798 	_clk_stm32_pll_disable(priv, pll);  in _clk_stm32_pll_init()
1805 	ret = clk_stm32_pll_wait_mux_ready(priv, pll);  in _clk_stm32_pll_init()
1810 	ret = clk_stm32_pll_config_output(priv, pll, pll_conf->cfg, pll_conf->frac);  in _clk_stm32_pll_init()
1816 		clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);  in _clk_stm32_pll_init()
1820 	_clk_stm32_pll_enable(priv, pll);  in _clk_stm32_pll_init()
2345 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)  in clk_stm32_parse_pll_fdt()  argument
2362 	err = fdt_read_uint32_array(fdt, subnode_pll, "cfg", (int)PLLCFG_NB, pll->cfg);  in clk_stm32_parse_pll_fdt()
2367 	err = fdt_read_uint32_array(fdt, subnode_pll, "csg", (int)PLLCSG_NB, pll->csg);  in clk_stm32_parse_pll_fdt()
2369 	pll->csg_enabled = (err == 0);  in clk_stm32_parse_pll_fdt()
2379 	pll->enabled = true;  in clk_stm32_parse_pll_fdt()
2381 	pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0);  in clk_stm32_parse_pll_fdt()
2383 	pll->src = UINT32_MAX;  in clk_stm32_parse_pll_fdt()
2387 		pll->src = val;  in clk_stm32_parse_pll_fdt()
2400 		struct stm32_pll_dt_cfg *pll = pdata->pll + i;  in stm32_clk_parse_fdt_all_pll()  local
2417 		err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);  in stm32_clk_parse_fdt_all_pll()
2492 	.pll = mp2_pll,