Merge changes from topic "stm32mp2_fixes" into integration

* changes:
fix(stm32mp2-fdts): set SDMMC max frequency to 166 MHz on stm32mp25
fix(stm32mp25-fdts): new swizzle configuration for STM32

Merge changes from topic "stm32mp2_fixes" into integration

* changes:
fix(stm32mp2-fdts): set SDMMC max frequency to 166 MHz on stm32mp25
fix(stm32mp25-fdts): new swizzle configuration for STM32MP257F-EV1 board
fix(st-clock): prevent panic when external oscillator is absent
feat(st-clock): rename RCC_USBTCCFGR register into RCC_UCPDCFGR
fix(dt-bindings): bad FLEXGEN configuration of pred-division for STM32MP25
fix(st-clock): force ARM_DIVSEL for flexgen63 config at 400MHz

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feat(st-clock): rename RCC_USBTCCFGR register into RCC_UCPDCFGR

Rename this register to be aligned with the reference manual.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change

feat(st-clock): rename RCC_USBTCCFGR register into RCC_UCPDCFGR

Rename this register to be aligned with the reference manual.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ia10c287bf4068742a7add9016c1a87e300eebff0

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fix(st-clock): force ARM_DIVSEL for flexgen63 config at 400MHz

The clkext2f frequency at 400MHZ, the default flexgen63 config,
is not supported without a divider by 2 as described in reference Manue

fix(st-clock): force ARM_DIVSEL for flexgen63 config at 400MHz

The clkext2f frequency at 400MHZ, the default flexgen63 config,
is not supported without a divider by 2 as described in reference Manuel,
chapter 3.3 Cortex-A35 clocking:

The clock for the Cortex-A35 subsystem can be selected among:
a clock from the device clock generator (aka ck_cpu1_ext2f). The maximum
frequency on this clock is 400 MHz with a divider by two, enabled thanks
to the CA35SS_SSC_CHGCLKREQ SSC register.

In OpenSTLinux clock tree you assume flexgen63 = 400MHz,
so we force divider by 2 for ck_cpu1_ext2f clock, the CA35 bypass clock
with ARM_DIVSEL = 0.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I9d11f9316ce3a2c7280a9bb7652d241b164ce5a1

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Merge "fix(st-clock): add ck_bus_risaf4 clock for STM32MP2" into integration

fix(st-clock): add ck_bus_risaf4 clock for STM32MP2

Add management of the ck_bus_risaf4 clock.
The RISAF4 clock is missing, which causes a panic if it is enabled.
The DDR clock is set to critical as

fix(st-clock): add ck_bus_risaf4 clock for STM32MP2

Add management of the ck_bus_risaf4 clock.
The RISAF4 clock is missing, which causes a panic if it is enabled.
The DDR clock is set to critical as it is mandatory to keep the DDR
clock active.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6ac2aff07484bfc22210ee9d3e46a97d1735f34b

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Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family

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feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32

feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32MP21,
STM32MP23 and STM32MP25 flags.
STM32MP23 will use the same RCC clock compatible of STM32MP25 SoC.

Change-Id: I6422cd0553067dc92f80da1ad8ec78cadf2432bb
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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Merge changes from topic "st_mp2_clk_reset" into integration

* changes:
feat(st-reset): add stm32mp2_reset driver
feat(st-clock): add STM32MP2 clock driver
fix(dt-bindings): update STM32MP2 cl

Merge changes from topic "st_mp2_clk_reset" into integration

* changes:
feat(st-reset): add stm32mp2_reset driver
feat(st-clock): add STM32MP2 clock driver
fix(dt-bindings): update STM32MP2 clock and reset bindings
feat(st-reset): add system reset management

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feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c689

feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c6897229276a150c0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

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