Merge "fix(stm32mp15-fdts): correct MCO2_PLL4 clock name for DHCOM" into integration

fix(stm32mp15-fdts): correct MCO2_PLL4 clock name for DHCOM

This clock name was renamed from MCO2_PLL4P to MCO2_PLL4 with the RCC
binding update commit [1]. This file was missed in that update, and

fix(stm32mp15-fdts): correct MCO2_PLL4 clock name for DHCOM

This clock name was renamed from MCO2_PLL4P to MCO2_PLL4 with the RCC
binding update commit [1]. This file was missed in that update, and the
board fails to compile.

[1]: 52b253bfa2 feat(dt-bindings): new RCC DT bindings

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I215abff1fc275ac1ef6dfb2ac86b9223e6990064

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Merge changes from topic "st_clk_update" into integration

* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct

Merge changes from topic "st_clk_update" into integration

* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct
feat(stm32mp1-fdts): remove RTC clock configuration
refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock
refactor(st-clock): driver size optimization
refactor(st-clock): remove BL32 support on STM32MP13
feat(st-clock): don't gate/ungate an oscillator if it is not wired
feat(dt-bindings): add missing SPIx bus clocks
feat(stm32mp1-fdts): remove PLL1 settings
feat(st-clock): update with new bindings
feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1
feat(dt-bindings): new RCC DT bindings
feat(stm32mp1): always boot at 650MHz
refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13
fix(st-clock): display proper PLL number for STM32MP13
fix(st-clock): do not reconfigure LSE
feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation
refactor(st-clock): remove unused clk function in API
refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config
feat(st-clock): add function to restore generic timer rate

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feat(stm32mp1-fdts): remove PLL1 settings

TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.

Change-Id: I0003337d8d37d

feat(stm32mp1-fdts): remove PLL1 settings

TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.

Change-Id: I0003337d8d37df7b2a70a84b5475f4278c4c4669
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1

RCC bindings alignment with MP13 RCC bindings

Change-Id: I02c89accd51e4214cd009d4a9433d8d9b6aeba25
Signed-off-by: Gabriel Fernandez <gabriel.fe

feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1

RCC bindings alignment with MP13 RCC bindings

Change-Id: I02c89accd51e4214cd009d4a9433d8d9b6aeba25
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation

LSI was too slow to provide enough random numbers (limited
to 6ms for 16 bytes production). Switch to CSI that allow
to get the RNG

feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation

LSI was too slow to provide enough random numbers (limited
to 6ms for 16 bytes production). Switch to CSI that allow
to get the RNG fifo ready in less than 50µs.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I76d1fe58e2f4d5416a96f48123ae36bd82d8a8ee

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Merge changes from topic "st-bsec-otp" into integration

* changes:
feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
fix(stm

Merge changes from topic "st-bsec-otp" into integration

* changes:
feat(stm32mp2-fdts): add board ID OTP in STM32MP257F-EV1
feat(stm32mp2-fdts): add OTP nodes in STM32MP251 SoC DT file
fix(stm32mp2): add missing include
feat(st): do not directly call BSEC functions in common code
feat(st): use stm32_get_otp_value_from_idx() in BL31
refactor(st): update test for closed chip
refactor(st-bsec): improve BSEC driver
refactor(st): use dashes for BSEC node names

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refactor(st): use dashes for BSEC node names

This is something commonly asked by Linux kernel DT maintainers [1].
The mentioned doc is not upstreamed, but may be checked with dtbs_check.
While at it

refactor(st): use dashes for BSEC node names

This is something commonly asked by Linux kernel DT maintainers [1].
The mentioned doc is not upstreamed, but may be checked with dtbs_check.
While at it align some nodes with Linux or OP-TEE.

[1] https://lore.kernel.org/linux-arm-kernel/20231125184422.12315-1-krzysztof.kozlowski@linaro.org/

Change-Id: I63e983c2a00eda3cd8b81c66c0cd1a97cf8249b7
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "feat(st): update STM32MP DT files" into integration

feat(st): update STM32MP DT files

This is an alignment with Linux DT files that have been merged in
stm32 tree [1], and will be in Linux 6.7.
The /omit-if-no-ref/ in overlay files are now removed, a

feat(st): update STM32MP DT files

This is an alignment with Linux DT files that have been merged in
stm32 tree [1], and will be in Linux 6.7.
The /omit-if-no-ref/ in overlay files are now removed, as already in
pinctrl files.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iab94b0ba7a4a0288ca53d1ae57ab590566967415

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Merge changes from topic "stm32mp15-dt-updates" into integration

* changes:
refactor(stm32mp15-fdts): remove timers15 node
refactor(stm32mp15-fdts): remove unused secure-status properties
refa

Merge changes from topic "stm32mp15-dt-updates" into integration

* changes:
refactor(stm32mp15-fdts): remove timers15 node
refactor(stm32mp15-fdts): remove unused secure-status properties
refactor(stm32mp15-fdts): remove RCC secure-status

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refactor(stm32mp15-fdts): remove unused secure-status properties

For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED)

refactor(stm32mp15-fdts): remove unused secure-status properties

For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED) if
secure-status property is omitted. This secure-status property can then
be removed in boards DT files for iwdg nodes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9f9360842d4d41288db0cf1b92063f347c72d137

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refactor(stm32mp15-fdts): remove RCC secure-status

The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.

refactor(stm32mp15-fdts): remove RCC secure-status

The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.

[1] 812daf916c ("feat(st): update the security based on new compatible")

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iff31044ade78dd9c432120dce65375fe2b0d36d6

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Merge changes Ie650728a,Ie2736ef4 into integration

* changes:
refactor(stm32mp1-fdts): add missing spaces for consistent codestyle
refactor(stm32mp1-fdts): drop unused DDR calibration result on

Merge changes Ie650728a,Ie2736ef4 into integration

* changes:
refactor(stm32mp1-fdts): add missing spaces for consistent codestyle
refactor(stm32mp1-fdts): drop unused DDR calibration result on DHCOM

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refactor(stm32mp1-fdts): add missing spaces for consistent codestyle

Change-Id: Ie650728a0c671f553679b050afd969ce604ca111
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

Merge "feat(stm32mp15-fdts): add support for STM32MP157C based DHCOM SoM on PDK2 board" into integration

feat(stm32mp15-fdts): add support for STM32MP157C based DHCOM SoM on PDK2 board

This is an SoM in SODIMM-200 format on an evaluation board called
"DHCOM Premium Developer Kit #2" (DHCOM PDK2 for sho

feat(stm32mp15-fdts): add support for STM32MP157C based DHCOM SoM on PDK2 board

This is an SoM in SODIMM-200 format on an evaluation board called
"DHCOM Premium Developer Kit #2" (DHCOM PDK2 for short). The SoM features an
STM32MP157C SoC with 1 GB DDR3, 8 GB eMMC, microSD and 2 MB SPI flash.
The baseboard has multiple UART, USB, SPI, and I2C ports/headers and several
other interfaces that are not important for TF-A.

These dts(i) files are based on DHCOM dt's from Linux 5.16 and U-Boot 2022.01.
The DRAM calibration values are taken from U-Boot 2022.01 and are optimized for
industrial temperature range above 85° C.

TF-A on this board was fully tested with the latest OP-TEE developer setup.

Change-Id: I696c01742954d761fbad312cd1059e3ab01fa93c
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

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