xref: /rk3399_ARM-atf/fdts/stm32mp157a-avenger96.dts (revision 78ff36192f7dd4defa874d8f4387ec94cfcd20ee)
1cdf3d1a9SManivannan Sadhasivam// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2cdf3d1a9SManivannan Sadhasivam/*
3cdf3d1a9SManivannan Sadhasivam * Copyright (C) Arrow Electronics 2019 - All Rights Reserved
4cdf3d1a9SManivannan Sadhasivam * Author: Botond Kardos <botond.kardos@arroweurope.com>
5cdf3d1a9SManivannan Sadhasivam *
6cdf3d1a9SManivannan Sadhasivam * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
7cdf3d1a9SManivannan Sadhasivam * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
8cdf3d1a9SManivannan Sadhasivam */
9cdf3d1a9SManivannan Sadhasivam
10cdf3d1a9SManivannan Sadhasivam/dts-v1/;
11cdf3d1a9SManivannan Sadhasivam
12277d6af5SYann Gautier#include "stm32mp157.dtsi"
13277d6af5SYann Gautier#include "stm32mp15-pinctrl.dtsi"
14277d6af5SYann Gautier#include "stm32mp15xxac-pinctrl.dtsi"
15277d6af5SYann Gautier#include <dt-bindings/clock/stm32mp1-clksrc.h>
16277d6af5SYann Gautier#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
17cdf3d1a9SManivannan Sadhasivam
18cdf3d1a9SManivannan Sadhasivam/ {
19cdf3d1a9SManivannan Sadhasivam	model = "Arrow Electronics STM32MP157A Avenger96 board";
20277d6af5SYann Gautier	compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
21cdf3d1a9SManivannan Sadhasivam
22cdf3d1a9SManivannan Sadhasivam	aliases {
23277d6af5SYann Gautier		mmc0 = &sdmmc1;
24cdf3d1a9SManivannan Sadhasivam		serial0 = &uart4;
25277d6af5SYann Gautier		serial1 = &uart7;
26cdf3d1a9SManivannan Sadhasivam	};
27cdf3d1a9SManivannan Sadhasivam
28cdf3d1a9SManivannan Sadhasivam	chosen {
29cdf3d1a9SManivannan Sadhasivam		stdout-path = "serial0:115200n8";
30cdf3d1a9SManivannan Sadhasivam	};
31cdf3d1a9SManivannan Sadhasivam
32277d6af5SYann Gautier	memory@c0000000 {
33277d6af5SYann Gautier		device_type = "memory";
34277d6af5SYann Gautier		reg = <0xc0000000 0x40000000>;
35277d6af5SYann Gautier	};
36cdf3d1a9SManivannan Sadhasivam};
37cdf3d1a9SManivannan Sadhasivam
38cdf3d1a9SManivannan Sadhasivam&i2c4 {
39cdf3d1a9SManivannan Sadhasivam	pinctrl-names = "default";
40cdf3d1a9SManivannan Sadhasivam	pinctrl-0 = <&i2c4_pins_a>;
41cdf3d1a9SManivannan Sadhasivam	i2c-scl-rising-time-ns = <185>;
42cdf3d1a9SManivannan Sadhasivam	i2c-scl-falling-time-ns = <20>;
43cdf3d1a9SManivannan Sadhasivam	status = "okay";
44cdf3d1a9SManivannan Sadhasivam
45cdf3d1a9SManivannan Sadhasivam	pmic: stpmic@33 {
46cdf3d1a9SManivannan Sadhasivam		compatible = "st,stpmic1";
47cdf3d1a9SManivannan Sadhasivam		reg = <0x33>;
48cdf3d1a9SManivannan Sadhasivam		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
49cdf3d1a9SManivannan Sadhasivam		interrupt-controller;
50cdf3d1a9SManivannan Sadhasivam		#interrupt-cells = <2>;
51cdf3d1a9SManivannan Sadhasivam		status = "okay";
52cdf3d1a9SManivannan Sadhasivam
53cdf3d1a9SManivannan Sadhasivam		st,main-control-register = <0x04>;
54cdf3d1a9SManivannan Sadhasivam		st,vin-control-register = <0xc0>;
55277d6af5SYann Gautier		st,usb-control-register = <0x30>;
56cdf3d1a9SManivannan Sadhasivam
57cdf3d1a9SManivannan Sadhasivam		regulators {
58cdf3d1a9SManivannan Sadhasivam			compatible = "st,stpmic1-regulators";
59cdf3d1a9SManivannan Sadhasivam			ldo1-supply = <&v3v3>;
60cdf3d1a9SManivannan Sadhasivam			ldo2-supply = <&v3v3>;
61cdf3d1a9SManivannan Sadhasivam			ldo3-supply = <&vdd_ddr>;
62cdf3d1a9SManivannan Sadhasivam			ldo5-supply = <&v3v3>;
63cdf3d1a9SManivannan Sadhasivam			ldo6-supply = <&v3v3>;
64277d6af5SYann Gautier			pwr_sw1-supply = <&bst_out>;
65277d6af5SYann Gautier			pwr_sw2-supply = <&bst_out>;
66cdf3d1a9SManivannan Sadhasivam
67cdf3d1a9SManivannan Sadhasivam			vddcore: buck1 {
68cdf3d1a9SManivannan Sadhasivam				regulator-name = "vddcore";
69cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <1200000>;
70cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <1350000>;
71cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
72cdf3d1a9SManivannan Sadhasivam				regulator-initial-mode = <0>;
73cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
74cdf3d1a9SManivannan Sadhasivam			};
75cdf3d1a9SManivannan Sadhasivam
76cdf3d1a9SManivannan Sadhasivam			vdd_ddr: buck2 {
77cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdd_ddr";
78cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <1350000>;
79cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <1350000>;
80cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
81cdf3d1a9SManivannan Sadhasivam				regulator-initial-mode = <0>;
82cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
83cdf3d1a9SManivannan Sadhasivam			};
84cdf3d1a9SManivannan Sadhasivam
85cdf3d1a9SManivannan Sadhasivam			vdd: buck3 {
86cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdd";
87cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <3300000>;
88cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <3300000>;
89cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
90cdf3d1a9SManivannan Sadhasivam				st,mask-reset;
91cdf3d1a9SManivannan Sadhasivam				regulator-initial-mode = <0>;
92cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
93cdf3d1a9SManivannan Sadhasivam			};
94cdf3d1a9SManivannan Sadhasivam
95cdf3d1a9SManivannan Sadhasivam			v3v3: buck4 {
96cdf3d1a9SManivannan Sadhasivam				regulator-name = "v3v3";
97cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <3300000>;
98cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <3300000>;
99cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
100cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
101cdf3d1a9SManivannan Sadhasivam				regulator-initial-mode = <0>;
102cdf3d1a9SManivannan Sadhasivam			};
103cdf3d1a9SManivannan Sadhasivam
104cdf3d1a9SManivannan Sadhasivam			vdda: ldo1 {
105cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdda";
106cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <2900000>;
107cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <2900000>;
108cdf3d1a9SManivannan Sadhasivam			};
109cdf3d1a9SManivannan Sadhasivam
110cdf3d1a9SManivannan Sadhasivam			v2v8: ldo2 {
111cdf3d1a9SManivannan Sadhasivam				regulator-name = "v2v8";
112cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <2800000>;
113cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <2800000>;
114cdf3d1a9SManivannan Sadhasivam			};
115cdf3d1a9SManivannan Sadhasivam
116cdf3d1a9SManivannan Sadhasivam			vtt_ddr: ldo3 {
117cdf3d1a9SManivannan Sadhasivam				regulator-name = "vtt_ddr";
118cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
119cdf3d1a9SManivannan Sadhasivam				regulator-over-current-protection;
1209eed71b7SAhmad Fatoum				st,regulator-sink-source;
121cdf3d1a9SManivannan Sadhasivam			};
122cdf3d1a9SManivannan Sadhasivam
123cdf3d1a9SManivannan Sadhasivam			vdd_usb: ldo4 {
124cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdd_usb";
125cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <3300000>;
126cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <3300000>;
127cdf3d1a9SManivannan Sadhasivam			};
128cdf3d1a9SManivannan Sadhasivam
129cdf3d1a9SManivannan Sadhasivam			vdd_sd: ldo5 {
130cdf3d1a9SManivannan Sadhasivam				regulator-name = "vdd_sd";
131cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <2900000>;
132cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <2900000>;
133cdf3d1a9SManivannan Sadhasivam				regulator-boot-on;
134cdf3d1a9SManivannan Sadhasivam			};
135cdf3d1a9SManivannan Sadhasivam
136cdf3d1a9SManivannan Sadhasivam			v1v8: ldo6 {
137cdf3d1a9SManivannan Sadhasivam				regulator-name = "v1v8";
138cdf3d1a9SManivannan Sadhasivam				regulator-min-microvolt = <1800000>;
139cdf3d1a9SManivannan Sadhasivam				regulator-max-microvolt = <1800000>;
140cdf3d1a9SManivannan Sadhasivam			};
141cdf3d1a9SManivannan Sadhasivam
142cdf3d1a9SManivannan Sadhasivam			vref_ddr: vref_ddr {
143cdf3d1a9SManivannan Sadhasivam				regulator-name = "vref_ddr";
144cdf3d1a9SManivannan Sadhasivam				regulator-always-on;
145cdf3d1a9SManivannan Sadhasivam			};
146277d6af5SYann Gautier
147277d6af5SYann Gautier			bst_out: boost {
148277d6af5SYann Gautier				regulator-name = "bst_out";
149277d6af5SYann Gautier			};
150277d6af5SYann Gautier
151277d6af5SYann Gautier			vbus_otg: pwr_sw1 {
152277d6af5SYann Gautier				regulator-name = "vbus_otg";
153277d6af5SYann Gautier			};
154277d6af5SYann Gautier
155277d6af5SYann Gautier			vbus_sw: pwr_sw2 {
156277d6af5SYann Gautier				regulator-name = "vbus_sw";
157277d6af5SYann Gautier				regulator-active-discharge = <1>;
158277d6af5SYann Gautier			};
159cdf3d1a9SManivannan Sadhasivam		};
160cdf3d1a9SManivannan Sadhasivam	};
161cdf3d1a9SManivannan Sadhasivam};
162cdf3d1a9SManivannan Sadhasivam
163cdf3d1a9SManivannan Sadhasivam&iwdg2 {
164cdf3d1a9SManivannan Sadhasivam	timeout-sec = <32>;
165cdf3d1a9SManivannan Sadhasivam	status = "okay";
166cdf3d1a9SManivannan Sadhasivam};
167cdf3d1a9SManivannan Sadhasivam
168277d6af5SYann Gautier&pwr_regulators {
169277d6af5SYann Gautier	vdd-supply = <&vdd>;
170277d6af5SYann Gautier	vdd_3v3_usbfs-supply = <&vdd_usb>;
171cdf3d1a9SManivannan Sadhasivam};
172cdf3d1a9SManivannan Sadhasivam
173cdf3d1a9SManivannan Sadhasivam&rcc {
174cdf3d1a9SManivannan Sadhasivam	st,clksrc = <
175cdf3d1a9SManivannan Sadhasivam		CLK_MPU_PLL1P
176cdf3d1a9SManivannan Sadhasivam		CLK_AXI_PLL2P
177cdf3d1a9SManivannan Sadhasivam		CLK_MCU_PLL3P
178cdf3d1a9SManivannan Sadhasivam		CLK_RTC_LSE
179cdf3d1a9SManivannan Sadhasivam		CLK_MCO1_DISABLED
180cdf3d1a9SManivannan Sadhasivam		CLK_MCO2_DISABLED
181cdf3d1a9SManivannan Sadhasivam		CLK_CKPER_HSE
182cdf3d1a9SManivannan Sadhasivam		CLK_FMC_ACLK
183cdf3d1a9SManivannan Sadhasivam		CLK_QSPI_ACLK
184cdf3d1a9SManivannan Sadhasivam		CLK_ETH_DISABLED
185cdf3d1a9SManivannan Sadhasivam		CLK_SDMMC12_PLL4P
186cdf3d1a9SManivannan Sadhasivam		CLK_DSI_DSIPLL
187cdf3d1a9SManivannan Sadhasivam		CLK_STGEN_HSE
188cdf3d1a9SManivannan Sadhasivam		CLK_USBPHY_HSE
189cdf3d1a9SManivannan Sadhasivam		CLK_SPI2S1_PLL3Q
190cdf3d1a9SManivannan Sadhasivam		CLK_SPI2S23_PLL3Q
191cdf3d1a9SManivannan Sadhasivam		CLK_SPI45_HSI
192cdf3d1a9SManivannan Sadhasivam		CLK_SPI6_HSI
193cdf3d1a9SManivannan Sadhasivam		CLK_I2C46_HSI
194cdf3d1a9SManivannan Sadhasivam		CLK_SDMMC3_PLL4P
195cdf3d1a9SManivannan Sadhasivam		CLK_USBO_USBPHY
196cdf3d1a9SManivannan Sadhasivam		CLK_ADC_CKPER
197cdf3d1a9SManivannan Sadhasivam		CLK_CEC_LSE
198cdf3d1a9SManivannan Sadhasivam		CLK_I2C12_HSI
199cdf3d1a9SManivannan Sadhasivam		CLK_I2C35_HSI
200cdf3d1a9SManivannan Sadhasivam		CLK_UART1_HSI
201cdf3d1a9SManivannan Sadhasivam		CLK_UART24_HSI
202cdf3d1a9SManivannan Sadhasivam		CLK_UART35_HSI
203cdf3d1a9SManivannan Sadhasivam		CLK_UART6_HSI
204cdf3d1a9SManivannan Sadhasivam		CLK_UART78_HSI
205cdf3d1a9SManivannan Sadhasivam		CLK_SPDIF_PLL4P
2062dc9fe70SAntonio Borneo		CLK_FDCAN_PLL4R
207cdf3d1a9SManivannan Sadhasivam		CLK_SAI1_PLL3Q
208cdf3d1a9SManivannan Sadhasivam		CLK_SAI2_PLL3Q
209cdf3d1a9SManivannan Sadhasivam		CLK_SAI3_PLL3Q
210cdf3d1a9SManivannan Sadhasivam		CLK_SAI4_PLL3Q
211d594239dSLionel Debieve		CLK_RNG1_CSI
212cdf3d1a9SManivannan Sadhasivam		CLK_RNG2_LSI
213cdf3d1a9SManivannan Sadhasivam		CLK_LPTIM1_PCLK1
214cdf3d1a9SManivannan Sadhasivam		CLK_LPTIM23_PCLK3
215cdf3d1a9SManivannan Sadhasivam		CLK_LPTIM45_LSE
216cdf3d1a9SManivannan Sadhasivam	>;
217cdf3d1a9SManivannan Sadhasivam
218*4391e5edSGabriel Fernandez	st,clkdiv = <
219*4391e5edSGabriel Fernandez		DIV(DIV_MPU, 1)
220*4391e5edSGabriel Fernandez		DIV(DIV_AXI, 0)
221*4391e5edSGabriel Fernandez		DIV(DIV_MCU, 0)
222*4391e5edSGabriel Fernandez		DIV(DIV_APB1, 1)
223*4391e5edSGabriel Fernandez		DIV(DIV_APB2, 1)
224*4391e5edSGabriel Fernandez		DIV(DIV_APB3, 1)
225*4391e5edSGabriel Fernandez		DIV(DIV_APB4, 1)
226*4391e5edSGabriel Fernandez		DIV(DIV_APB5, 2)
227*4391e5edSGabriel Fernandez		DIV(DIV_RTC, 23)
228*4391e5edSGabriel Fernandez		DIV(DIV_MCO1, 0)
229*4391e5edSGabriel Fernandez		DIV(DIV_MCO2, 0)
230*4391e5edSGabriel Fernandez	>;
231*4391e5edSGabriel Fernandez
232*4391e5edSGabriel Fernandez	st,pll_vco {
233*4391e5edSGabriel Fernandez		pll2_vco_1066Mhz: pll2-vco-1066Mhz {
234*4391e5edSGabriel Fernandez			src = <CLK_PLL12_HSE>;
235*4391e5edSGabriel Fernandez			divmn = <2 65>;
236*4391e5edSGabriel Fernandez			frac = <0x1400>;
237*4391e5edSGabriel Fernandez		};
238*4391e5edSGabriel Fernandez
239*4391e5edSGabriel Fernandez		pll3_vco_417Mhz: pll3-vco-417Mhz {
240*4391e5edSGabriel Fernandez			src = <CLK_PLL3_HSE>;
241*4391e5edSGabriel Fernandez			divmn = <1 33>;
242*4391e5edSGabriel Fernandez			frac = <0x1a04>;
243*4391e5edSGabriel Fernandez		};
244*4391e5edSGabriel Fernandez
245*4391e5edSGabriel Fernandez		pll4_vco_480Mhz: pll4-vco-480Mhz {
246*4391e5edSGabriel Fernandez			src = <CLK_PLL4_HSE>;
247*4391e5edSGabriel Fernandez			divmn = <1 39>;
248*4391e5edSGabriel Fernandez		};
249*4391e5edSGabriel Fernandez	};
250*4391e5edSGabriel Fernandez
251cdf3d1a9SManivannan Sadhasivam	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
252cdf3d1a9SManivannan Sadhasivam	pll2: st,pll@1 {
253277d6af5SYann Gautier		compatible = "st,stm32mp1-pll";
254277d6af5SYann Gautier		reg = <1>;
255*4391e5edSGabriel Fernandez
256*4391e5edSGabriel Fernandez		st,pll = <&pll2_cfg1>;
257*4391e5edSGabriel Fernandez
258*4391e5edSGabriel Fernandez		pll2_cfg1: pll2_cfg1 {
259*4391e5edSGabriel Fernandez			st,pll_vco = <&pll2_vco_1066Mhz>;
260*4391e5edSGabriel Fernandez			st,pll_div_pqr = <1 0 0>;
261*4391e5edSGabriel Fernandez		};
262cdf3d1a9SManivannan Sadhasivam	};
263cdf3d1a9SManivannan Sadhasivam
264cdf3d1a9SManivannan Sadhasivam	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
265cdf3d1a9SManivannan Sadhasivam	pll3: st,pll@2 {
266277d6af5SYann Gautier		compatible = "st,stm32mp1-pll";
267277d6af5SYann Gautier		reg = <2>;
268*4391e5edSGabriel Fernandez
269*4391e5edSGabriel Fernandez		st,pll = <&pll3_cfg1>;
270*4391e5edSGabriel Fernandez
271*4391e5edSGabriel Fernandez		pll3_cfg1: pll3_cfg1 {
272*4391e5edSGabriel Fernandez			st,pll_vco = <&pll3_vco_417Mhz>;
273*4391e5edSGabriel Fernandez			st,pll_div_pqr = <1 16 36>;
274*4391e5edSGabriel Fernandez		};
275cdf3d1a9SManivannan Sadhasivam	};
276cdf3d1a9SManivannan Sadhasivam
277cdf3d1a9SManivannan Sadhasivam	/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
278cdf3d1a9SManivannan Sadhasivam	pll4: st,pll@3 {
279277d6af5SYann Gautier		compatible = "st,stm32mp1-pll";
280277d6af5SYann Gautier		reg = <3>;
281*4391e5edSGabriel Fernandez
282*4391e5edSGabriel Fernandez		st,pll = <&pll4_cfg1>;
283*4391e5edSGabriel Fernandez
284*4391e5edSGabriel Fernandez		pll4_cfg1: pll4_cfg1 {
285*4391e5edSGabriel Fernandez			st,pll_vco = <&pll4_vco_480Mhz>;
286*4391e5edSGabriel Fernandez			st,pll_div_pqr = <3 11 4>;
287*4391e5edSGabriel Fernandez		};
288cdf3d1a9SManivannan Sadhasivam	};
289cdf3d1a9SManivannan Sadhasivam};
290277d6af5SYann Gautier
291277d6af5SYann Gautier&rng1 {
292277d6af5SYann Gautier	status = "okay";
293277d6af5SYann Gautier};
294277d6af5SYann Gautier
295277d6af5SYann Gautier&rtc {
296277d6af5SYann Gautier	status = "okay";
297277d6af5SYann Gautier};
298277d6af5SYann Gautier
299277d6af5SYann Gautier&sdmmc1 {
300277d6af5SYann Gautier	pinctrl-names = "default";
301277d6af5SYann Gautier	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
302277d6af5SYann Gautier	st,sig-dir;
303277d6af5SYann Gautier	st,neg-edge;
304277d6af5SYann Gautier	st,use-ckin;
305277d6af5SYann Gautier	bus-width = <4>;
306277d6af5SYann Gautier	vmmc-supply = <&vdd_sd>;
307277d6af5SYann Gautier	status = "okay";
308277d6af5SYann Gautier};
309277d6af5SYann Gautier
310277d6af5SYann Gautier&uart4 {
311277d6af5SYann Gautier	/* On Low speed expansion header */
312277d6af5SYann Gautier	label = "LS-UART1";
313277d6af5SYann Gautier	pinctrl-names = "default";
314277d6af5SYann Gautier	pinctrl-0 = <&uart4_pins_b>;
315277d6af5SYann Gautier	status = "okay";
316277d6af5SYann Gautier};
317277d6af5SYann Gautier
318277d6af5SYann Gautier&uart7 {
319277d6af5SYann Gautier	/* On Low speed expansion header */
320277d6af5SYann Gautier	label = "LS-UART0";
321277d6af5SYann Gautier	pinctrl-names = "default";
322277d6af5SYann Gautier	pinctrl-0 = <&uart7_pins_a>;
323277d6af5SYann Gautier	status = "okay";
324277d6af5SYann Gautier};
325