82 	struct stm32_pll_dt_cfg *pll;  member
1194 				       const struct stm32_clk_pll *pll,  in clk_stm32_pll_compute_cfgr1()  argument
1203 	prate = _clk_stm32_get_parent_rate(priv, pll->clk_id);  in clk_stm32_pll_compute_cfgr1()
1206 	if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) ||  in clk_stm32_pll_compute_cfgr1()
1207 	    (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) {  in clk_stm32_pll_compute_cfgr1()
1213 	if ((pll->plltype == PLL_800) && (refclk >= 8000000U)) {  in clk_stm32_pll_compute_cfgr1()
1235 				     const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_vco()  argument
1238 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_vco()
1241 	if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) {  in clk_stm32_pll_config_vco()
1258 				     const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_csg()  argument
1261 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_csg()
1283 static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_out()  argument
1286 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_out()
1299 	return &pdata->pll[pll_idx];  in clk_stm32_pll_get_pdata()
1419 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_is_enabled()  argument
1421 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_is_enabled()
1426 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_set_on()  argument
1428 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_set_on()
1435 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_set_off()  argument
1437 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_set_off()
1447 					const struct stm32_clk_pll *pll)  in _clk_stm32_pll_wait_ready_on()  argument
1449 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_wait_ready_on()
1456 			      pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));  in _clk_stm32_pll_wait_ready_on()
1465 					 const struct stm32_clk_pll *pll)  in _clk_stm32_pll_wait_ready_off()  argument
1467 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_wait_ready_off()
1474 			      pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));  in _clk_stm32_pll_wait_ready_off()
1482 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_enable()  argument
1484 	if (_clk_stm32_pll_is_enabled(priv, pll)) {  in _clk_stm32_pll_enable()
1489 	_clk_stm32_pll_set_on(priv, pll);  in _clk_stm32_pll_enable()
1492 	return _clk_stm32_pll_wait_ready_on(priv, pll);  in _clk_stm32_pll_enable()
1495 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_disable()  argument
1497 	if (!_clk_stm32_pll_is_enabled(priv, pll)) {  in _clk_stm32_pll_disable()
1502 	_clk_stm32_pll_set_off(priv, pll);  in _clk_stm32_pll_disable()
1505 	_clk_stm32_pll_wait_ready_off(priv, pll);  in _clk_stm32_pll_disable()
1511 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_idx);  in _clk_stm32_pll_init()  local
1512 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_init()
1523 		clk_stm32_pll_config_out(priv, pll, &pll_conf->output);  in _clk_stm32_pll_init()
1532 	_clk_stm32_pll_disable(priv, pll);  in _clk_stm32_pll_init()
1534 	clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);  in _clk_stm32_pll_init()
1535 	clk_stm32_pll_config_out(priv, pll, &pll_conf->output);  in _clk_stm32_pll_init()
1536 	clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco);  in _clk_stm32_pll_init()
1538 	ret = _clk_stm32_pll_enable(priv, pll);  in _clk_stm32_pll_init()
1704 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);  in clk_stm32_pll_recalc_rate()  local
1705 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_recalc_rate()
1741 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);  in clk_stm32_pll_is_enabled()  local
1743 	return _clk_stm32_pll_is_enabled(priv, pll);  in clk_stm32_pll_is_enabled()
1750 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);  in clk_stm32_pll_enable()  local
1752 	return _clk_stm32_pll_enable(priv, pll);  in clk_stm32_pll_enable()
1759 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);  in clk_stm32_pll_disable()  local
1761 	_clk_stm32_pll_disable(priv, pll);  in clk_stm32_pll_disable()
1998 	.pll		= mp13_pll,
2230 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)  in clk_stm32_parse_pll_fdt()  argument
2257 	err = clk_stm32_load_vco_config(fdt, subnode_vco, &pll->vco);  in clk_stm32_parse_pll_fdt()
2262 	err = clk_stm32_load_output_config(fdt, subnode_pll, &pll->output);  in clk_stm32_parse_pll_fdt()
2276 		struct stm32_pll_dt_cfg *pll = &pdata->pll[i];  in stm32_clk_parse_fdt_all_pll()  local
2288 		err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);  in stm32_clk_parse_fdt_all_pll()