Merge changes from topic "nxp-clk/add_usdhc_clock" into integration

* changes:
feat(s32g274a): enable sdhc clock
feat(nxp-clk): add clock modules for uSDHC
feat(nxp-clk): get MC_CGM divider's

Merge changes from topic "nxp-clk/add_usdhc_clock" into integration

* changes:
feat(s32g274a): enable sdhc clock
feat(nxp-clk): add clock modules for uSDHC
feat(nxp-clk): get MC_CGM divider's parent
feat(nxp-clk): get MC_CGM divider's rate
feat(nxp-clk): set MC_CGM divider's rate
feat(nxp-clk): enable MC_CGM dividers
feat(nxp-clk): get parent for the fixed dividers
feat(nxp-clk): set the rate for partition objects
feat(nxp-clk): add clock objects for CGM dividers
feat(nxp-clk): add base address for PERIPH_DFS

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feat(nxp-clk): get MC_CGM divider's parent

The parent of the MC_CGM divider will always be the MC_CGM mux
identified based on s32cc_cgm_div.parent.

Change-Id: Ie13b16e0ee56f35d61374efbe158f166b9996

feat(nxp-clk): get MC_CGM divider's parent

The parent of the MC_CGM divider will always be the MC_CGM mux
identified based on s32cc_cgm_div.parent.

Change-Id: Ie13b16e0ee56f35d61374efbe158f166b99960b7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get MC_CGM divider's rate

The MC_CGM divider's frequency is obtained based on the state of the
settings found in its registers. If the divider is disabled, the
intended rate (s32cc_cg

feat(nxp-clk): get MC_CGM divider's rate

The MC_CGM divider's frequency is obtained based on the state of the
settings found in its registers. If the divider is disabled, the
intended rate (s32cc_cgm_div.freq) will be returned.

Change-Id: I41698990952b530021de26eb51f74aca50176575
Co-developed-by: Florin Buica <florin.buica@nxp.com>
Signed-off-by: Florin Buica <florin.buica@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set MC_CGM divider's rate

The MC_CGM divider's frequency is saved as part of the object metadata.
No checks are performed on the requested frequency. It will be validated
during the e

feat(nxp-clk): set MC_CGM divider's rate

The MC_CGM divider's frequency is saved as part of the object metadata.
No checks are performed on the requested frequency. It will be validated
during the enablement process.

Change-Id: Ide9c8c64be16a66b66f129735cebfc4d1f1772c5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable MC_CGM dividers

Add the enablement mechanism for the MC_CGM dividers. The division
factor is established by dividing the parent's rate by the rate of the
divider's output.

Cha

feat(nxp-clk): enable MC_CGM dividers

Add the enablement mechanism for the MC_CGM dividers. The division
factor is established by dividing the parent's rate by the rate of the
divider's output.

Change-Id: Iadb84f4f47531a67b0b1509b94e1f2b962631a77
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get parent for the fixed dividers

Fixed dividers contribute to the Linflex and QSPI clocks.

Change-Id: Idb4e6fe883e117b2bb9260b6eeb6e15d75ce887e
Signed-off-by: Ghennadi Procopciuc <g

feat(nxp-clk): get parent for the fixed dividers

Fixed dividers contribute to the Linflex and QSPI clocks.

Change-Id: Idb4e6fe883e117b2bb9260b6eeb6e15d75ce887e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set the rate for partition objects

Only the partition block link can set the frequency, while the other two
should not be able to because none of them participate in the clock
generat

feat(nxp-clk): set the rate for partition objects

Only the partition block link can set the frequency, while the other two
should not be able to because none of them participate in the clock
generation. In the first case, the request will be propagated to the
parent object of the partition link.

Change-Id: Ic237972008eb51c62e92f03f657698a8a1ca4b0e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: I

feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: Id2786a46c5a1d389ca32a4839c7158949aec3b0a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-clk/add_get_rate" into integration

* changes:
feat(nxp-clk): restore pll output dividers rate
feat(nxp-clk): get pll rate using get_module_rate
feat(nxp-clk): add

Merge changes from topic "nxp-clk/add_get_rate" into integration

* changes:
feat(nxp-clk): restore pll output dividers rate
feat(nxp-clk): get pll rate using get_module_rate
feat(nxp-clk): add get_rate for partition objects
feat(nxp-clk): add get_rate for clock muxes
feat(nxp-clk): add get_rate for s32cc_pll_out_div
feat(nxp-clk): add get_rate for s32cc_fixed_div
feat(nxp-clk): add get_rate for s32cc_dfs_div
feat(nxp-clk): add get_rate for s32cc_dfs
feat(nxp-clk): add get_rate for s32cc_pll
feat(nxp-clk): add get_rate for s32cc_clk
feat(nxp-clk): add a basic get_rate implementation

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feat(nxp-clk): restore pll output dividers rate

Reconfiguration of the PLL may be requested while some output dividers
are already enabled. To prevent setting a different frequency for these
enabled

feat(nxp-clk): restore pll output dividers rate

Reconfiguration of the PLL may be requested while some output dividers
are already enabled. To prevent setting a different frequency for these
enabled dividers, the driver will attempt to adjust the division factor
to achieve the initially requested rate.

Change-Id: I7800c05b2f21bbdeda243db865942b647983687d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get pll rate using get_module_rate

The DFS can use the get_module_rate instead of assuming its parent
object is a PLL. It also has the advantage that the frequency will be
returned ba

feat(nxp-clk): get pll rate using get_module_rate

The DFS can use the get_module_rate instead of assuming its parent
object is a PLL. It also has the advantage that the frequency will be
returned based on the hardware state of the PLL module.

Change-Id: I3a270cbc92622ae82606382df1301597dc29782a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for partition objects

The partition-related objects do not participate in clock rate
calculation, except the s32cc_part_block_link_t, whose call is forwarded
to the paren

feat(nxp-clk): add get_rate for partition objects

The partition-related objects do not participate in clock rate
calculation, except the s32cc_part_block_link_t, whose call is forwarded
to the parent object.

Change-Id: Id9e7fa49c3c1fb5b30b4c1b97fc8441bc967578a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for clock muxes

From the get rate callback perspective, all types of clock muxes should
return the frequency of the selected source, regardless of whether it is
an MC_CGM

feat(nxp-clk): add get_rate for clock muxes

From the get rate callback perspective, all types of clock muxes should
return the frequency of the selected source, regardless of whether it is
an MC_CGM or PLL mux.

Change-Id: I24ae821013b0844e4d62793fde12b53b043a9776
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_pll_out_div

The get rate callback is needed for s32cc_pll_out_div to get the A53
cores and DDR rate.

Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4
Signe

feat(nxp-clk): add get_rate for s32cc_pll_out_div

The get rate callback is needed for s32cc_pll_out_div to get the A53
cores and DDR rate.

Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_fixed_div

The get rate callback is needed for s32cc_fixed_div to allow the
frequency compilation for modules attached to a fixed divider like
LINFLEXD_CLK.

Cha

feat(nxp-clk): add get_rate for s32cc_fixed_div

The get rate callback is needed for s32cc_fixed_div to allow the
frequency compilation for modules attached to a fixed divider like
LINFLEXD_CLK.

Change-Id: Ibc3e52f7f1127bba0dd793be0a26bdff15260824
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_dfs_div

Add the option to obtain the rate of an s32cc_dfs_div object. As in the
case of the PLL, the output divider of a DFS will return its targeted
frequency

feat(nxp-clk): add get_rate for s32cc_dfs_div

Add the option to obtain the rate of an s32cc_dfs_div object. As in the
case of the PLL, the output divider of a DFS will return its targeted
frequency if the module is disabled and calculate the rate based on the
settings found in its registers if the module is turned on.

Change-Id: Id6db92dbdf03f8119875476ad8f7aa268ff6ea93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_dfs

Add the option to obtain the rate of an s32cc_dfs object. The DFS rate
depends on the module to which it's connected. Therefore, it will always
return the r

feat(nxp-clk): add get_rate for s32cc_dfs

Add the option to obtain the rate of an s32cc_dfs object. The DFS rate
depends on the module to which it's connected. Therefore, it will always
return the rate of its parent.

Change-Id: Ie3becd36721f541d0fab11b2fb57aacd66d48220
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_pll

Add the option to obtain the rate of an s32cc_pll object. The rate of
the PLL can be obtained regardless of its hardware state. The targeted
frequency is re

feat(nxp-clk): add get_rate for s32cc_pll

Add the option to obtain the rate of an s32cc_pll object. The rate of
the PLL can be obtained regardless of its hardware state. The targeted
frequency is returned in case the PLL is off. Otherwise, the frequency
is determined based on settings found in its registers.

Change-Id: Id200d0eff149109a724eee69b063bf750d5cba2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_clk

Add the option to obtain the rate of an s32cc_clk object. s32cc_clk are
usually links to either another s32cc_clk or a different clock module.
Therefore, th

feat(nxp-clk): add get_rate for s32cc_clk

Add the option to obtain the rate of an s32cc_clk object. s32cc_clk are
usually links to either another s32cc_clk or a different clock module.
Therefore, this function routes the request.

Change-Id: I0c1174cb861d2062882319e46cb6ca97bad70aab
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add mor

feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add more objects to this list.

Change-Id: I8c1bbbfa6b116fdcf5a1f1353bdb52b474bac831
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-s32g274a/enable-mmu" into integration

* changes:
feat(s32g274a): split early clock initialization
feat(s32g274a): enable MMU for BL31 stage
feat(s32g274a): dynami

Merge changes from topic "nxp-s32g274a/enable-mmu" into integration

* changes:
feat(s32g274a): split early clock initialization
feat(s32g274a): enable MMU for BL31 stage
feat(s32g274a): dynamically map GIC regions
feat(s32g274a): enable MMU for BL2 stage
feat(s32g274a): dynamically map siul2 and fip img
feat(s32g274a): map each image before its loading
feat(nxp-clk): dynamic map of the clock modules
feat(s32g274a): increase the number of MMU regions
feat(s32g274a): add console mapping

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feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks ca

feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.

Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add object

Merge changes from topic "nxp-clk/add_ddr_clk" into integration

* changes:
fix(nxp-clk): function parameter should not be modified
feat(nxp-clk): enable the DDR clock
feat(nxp-clk): add objects needed for DDR clock
feat(nxp-clk): setup the DDR PLL
feat(nxp-clk): add MC_ME utilities
feat(nxp-clk): add partition reset utilities
feat(nxp-clk): add partitions objects

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