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/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/
H A Dnrd_css_def3.h18 #define NRD_CSS_SHARED_SRAM_BASE UL(0x00000000)
21 #define NRD_CSS_PERIPH_BASE UL(0x20000000)
22 #define NRD_CSS_PERIPH_SIZE UL(0x20000000)
25 #define NRD_CSS_SYSTEM_NCI_BASE UL(0x20000000)
26 #define NRD_CSS_SYSTEM_NCI_SIZE UL(0x04000000)
29 #define NRD_CSS_DEBUG_NIC_BASE UL(0x28000000)
30 #define NRD_CSS_DEBUG_NIC_SIZE UL(0x01000000)
33 #define NRD_CSS_NS_UART_BASE UL(0x2A400000)
34 #define NRD_CSS_NS_UART_SIZE UL(0x00010000)
37 #define NRD_CSS_SECURE_UART_BASE UL(0x2A410000)
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H A Dnrd_css_fw_def3.h19 #define NRD_CSS_BL1_RW_SIZE UL(64 * 1024) /* 64KB */
22 #define NRD_CSS_BL1_RO_SIZE UL(0x00019000)
24 # define NRD_CSS_BL2_SIZE UL(0x30000)
34 #define NRD_CSS_BL31_SIZE UL(116 * 1024) /* 116 KB */
36 #define NRD_CSS_DRAM1_CARVEOUT_SIZE UL(0x0C000000) /* 192MB */
42 #define NRD_CSS_UART_CLK_IN_HZ UL(7372800)
48 #define NRD_CSS_AP_SECURE_WDOG_TIMEOUT UL(100)
56 #define NRD_CSS_RMM_CONSOLE_CLK_IN_HZ UL(14745600)
58 #define NRD_CSS_RMM_CONSOLE_COUNT UL(1)
134 #define NRD_CSS_BL31_PRELOAD_DTB_BASE UL(0xF3000000)
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/rk3399_ARM-atf/plat/amlogic/g12a/
H A Dg12a_def.h20 #define AML_HDCP_RX_BASE UL(0xFFE0D000)
21 #define AML_HDCP_RX_SIZE UL(0x00002000)
23 #define AML_HDCP_TX_BASE UL(0xFFE01000)
24 #define AML_HDCP_TX_SIZE UL(0x00001000)
26 #define AML_NS_SHARE_MEM_BASE UL(0x05000000)
27 #define AML_NS_SHARE_MEM_SIZE UL(0x00100000)
29 #define AML_SEC_SHARE_MEM_BASE UL(0x05200000)
30 #define AML_SEC_SHARE_MEM_SIZE UL(0x00100000)
32 #define AML_GIC_DEVICE_BASE UL(0xFFC00000)
33 #define AML_GIC_DEVICE_SIZE UL(0x00008000)
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/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_def.h39 #define FLASH1_BASE UL(0x0c000000)
40 #define FLASH1_SIZE UL(0x04000000)
42 #define PSRAM_BASE UL(0x14000000)
43 #define PSRAM_SIZE UL(0x04000000)
45 #define VRAM_BASE UL(0x18000000)
46 #define VRAM_SIZE UL(0x02000000)
49 #define DEVICE0_BASE UL(0x20000000)
50 #define DEVICE0_SIZE UL(0x0c200000)
56 #define CCN_BASE UL(0x2e000000)
57 #define CCN_SIZE UL(0x1000000)
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/rk3399_ARM-atf/plat/amlogic/gxbb/
H A Dgxbb_def.h20 #define AML_NSDRAM0_BASE UL(0x01000000)
21 #define AML_NSDRAM0_SIZE UL(0x0F000000)
23 #define AML_NSDRAM1_BASE UL(0x10000000)
24 #define AML_NSDRAM1_SIZE UL(0x00100000)
26 #define BL31_BASE UL(0x10100000)
27 #define BL31_SIZE UL(0x000C0000)
31 #define AML_SHARE_MEM_INPUT_BASE UL(0x100FE000)
32 #define AML_SHARE_MEM_OUTPUT_BASE UL(0x100FF000)
34 #define AML_SEC_DEVICE0_BASE UL(0xC0000000)
35 #define AML_SEC_DEVICE0_SIZE UL(0x09000000)
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/rk3399_ARM-atf/plat/amlogic/axg/
H A Daxg_def.h20 #define AML_NS_SHARE_MEM_BASE UL(0x05000000)
21 #define AML_NS_SHARE_MEM_SIZE UL(0x00100000)
23 #define AML_SEC_SHARE_MEM_BASE UL(0x05200000)
24 #define AML_SEC_SHARE_MEM_SIZE UL(0x00100000)
26 #define AML_GIC_DEVICE_BASE UL(0xFFC00000)
27 #define AML_GIC_DEVICE_SIZE UL(0x00008000)
29 #define AML_NSDRAM0_BASE UL(0x01000000)
30 #define AML_NSDRAM0_SIZE UL(0x0F000000)
32 #define BL31_BASE UL(0x05100000)
33 #define BL31_SIZE UL(0x00100000)
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/rk3399_ARM-atf/plat/amlogic/gxl/
H A Dgxl_def.h20 #define AML_NSDRAM0_BASE UL(0x01000000)
21 #define AML_NSDRAM0_SIZE UL(0x0F000000)
23 #define AML_NSDRAM1_BASE UL(0x10000000)
24 #define AML_NSDRAM1_SIZE UL(0x00100000)
26 #define BL31_BASE UL(0x05100000)
27 #define BL31_SIZE UL(0x000C0000)
31 #define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000)
32 #define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
34 #define AML_SEC_DEVICE0_BASE UL(0xC0000000)
35 #define AML_SEC_DEVICE0_SIZE UL(0x09000000)
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/rk3399_ARM-atf/plat/renesas/rcar_gen5/include/
H A Drcar_def.h13 #define RCAR_DOMAIN UL(0x0)
15 #define RCAR_TRUSTED_SRAM_BASE UL(0x8C200000) /* DRAM */
16 #define RCAR_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256kB */
19 #define RCAR_SHARED_MEM_SIZE UL(0x00002000) /* 8kB */
21 #define RCAR_BL31_CRASH_SIZE UL(0x00001000)
22 #define DEVICE_RCAR_BASE1 UL(0x10000000)
23 #define DEVICE_RCAR_SIZE1 UL(0x30000000)
24 #define DEVICE_RCAR_BASE2 UL(0xC0000000)
25 #define DEVICE_RCAR_SIZE2 UL(0x00C00000)
26 #define DEVICE_SRAM_BASE UL(0xE9042000)
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/rk3399_ARM-atf/plat/renesas/rcar_gen4/include/
H A Drcar_def.h13 #define RCAR_DOMAIN UL(0x0)
15 #define RCAR_TRUSTED_SRAM_BASE UL(0x46400000)
16 #define RCAR_TRUSTED_SRAM_SIZE UL(0x00022000)
19 #define RCAR_SHARED_MEM_SIZE UL(0x00001000)
20 #define RCAR_BL31_CRASH_BASE (RCAR_TRUSTED_SRAM_BASE + UL(0x3F000))
21 #define RCAR_BL31_CRASH_SIZE UL(0x00001000)
22 #define DEVICE_RCAR_BASE UL(0xE6000000)
23 #define DEVICE_RCAR_SIZE UL(0x00300000)
24 #define DEVICE_SRAM_BASE UL(0xE6342000)
25 #define DEVICE_SRAM_SIZE UL(0x00002000)
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/rk3399_ARM-atf/include/plat/common/
H A Dcommon_def.h16 #define SZ_32 UL(0x00000020)
17 #define SZ_64 UL(0x00000040)
18 #define SZ_128 UL(0x00000080)
19 #define SZ_256 UL(0x00000100)
20 #define SZ_512 UL(0x00000200)
22 #define SZ_1K UL(0x00000400)
23 #define SZ_2K UL(0x00000800)
24 #define SZ_4K UL(0x00001000)
25 #define SZ_8K UL(0x00002000)
26 #define SZ_16K UL(0x00004000)
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/rk3399_ARM-atf/services/std_svc/rmmd/trp/
H A Dtrp_main.c107 if ((x2 | x3) != 0UL) { in trp_validate_warmboot_args()
161 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL)); in trp_asc_mark_realm()
177 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL)); in trp_asc_mark_nonsecure()
218 ifvqw1, 0UL, 0UL)); in trp_ide_keymgmt_interface_fn()
223 ide_stream_info, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL)); in trp_ide_keymgmt_interface_fn()
228 ide_stream_info, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL)); in trp_ide_keymgmt_interface_fn()
233 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL)); in trp_ide_keymgmt_interface_fn()
/rk3399_ARM-atf/plat/arm/board/morello/
H A Dmorello_def.h11 #define MORELLO_NS_SRAM_BASE UL(0x06000000)
12 #define MORELLO_NS_SRAM_SIZE UL(0x00010000)
44 #define MORELLO_PLATFORM_INFO_BASE UL(0x06000000)
47 #define MORELLO_DMC0_MEMC_STATUS_REG UL(0x4E000000)
48 #define MORELLO_DMC1_MEMC_STATUS_REG UL(0x4E100000)
53 #define MORELLO_DMC0_MEMC_CMD_REG UL(0x4E000008)
54 #define MORELLO_DMC1_MEMC_CMD_REG UL(0x4E100008)
57 #define MORELLO_DMC0_CAP_CTRL_REG UL(0x4E000D00)
58 #define MORELLO_DMC1_CAP_CTRL_REG UL(0x4E100D00)
61 #define MORELLO_DMC0_TAG_CACHE_CTL UL(0x4E000D04)
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/rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rdaspen/include/
H A Dplatform_def.h13 #define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x0)
14 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00100000)
22 #define PLAT_ARM_SYS_CNTCTL_BASE UL(0x40000000)
24 #define PLAT_ARM_SYS_CNTREAD_BASE UL(0x40010000)
26 #define SI_MHU_REGION_BASE UL(0x40020000)
28 #define RDASPEN_CSS_AP_RSE_SECURE_MHU_BASE UL(0x40680000)
31 #define PLAT_ARM_SYS_TIMCTL_BASE UL(0x1A810000)
32 #define PLAT_ARM_SYS_CNT_BASE_S UL(0x1A820000)
33 #define PLAT_ARM_SYS_CNT_BASE_NS UL(0x1A830000)
84 #define PLATFORM_STACK_SIZE UL(0x1000)
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/rk3399_ARM-atf/include/plat/arm/board/common/
H A Dv2m_def.h15 #define V2M_OFFSET UL(0)
19 #define V2M_SYSREGS_BASE UL(0x1c010000)
20 #define V2M_SYSREGS_SIZE UL(0x00010000)
21 #define V2M_SYS_ID UL(0x0)
22 #define V2M_SYS_SWITCH UL(0x4)
23 #define V2M_SYS_LED UL(0x8)
24 #define V2M_SYS_NVFLAGS UL(0x38)
25 #define V2M_SYS_NVFLAGSSET UL(0x38)
26 #define V2M_SYS_NVFLAGSCLR UL(0x3c)
27 #define V2M_SYS_CFGDATA UL(0xa0)
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/rk3399_ARM-atf/plat/arm/board/juno/include/
H A Dplatform_def.h59 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */
65 #define NSRAM_BASE UL(0x2e000000)
66 #define NSRAM_SIZE UL(0x00008000) /* 32KB */
93 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
100 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
101 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
102 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000)
104 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
105 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
106 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0)
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/rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rd1ae/include/
H A Dplatform_def.h14 #define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x0)
25 #define PLATFORM_STACK_SIZE UL(0x1000)
28 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x0)
29 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x0)
31 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000)
45 #define PLAT_CSS_MHU_BASE UL(0x2A920000)
48 #define PLAT_ARM_SPMC_BASE UL(0xFFC00000)
49 #define PLAT_ARM_SPMC_SIZE UL(0x00400000)
51 #define SOC_CSS_SEC_UART_BASE UL(0x2A410000)
52 #define SOC_CSS_NSEC_UART_BASE UL(0x2A400000)
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/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd2/
H A Dnrd_ros_def2.h18 #define NRD_ROS_SYSTEMREG_BASE UL(0x0C010000)
19 #define NRD_ROS_SYSTEMREG_SIZE UL(0x00010000)
23 #define NRD_ROS_NOR2_FLASH_SIZE UL(0x000004000000)
26 #define NRD_ROS_MEMCNTRL_BASE UL(0x10000000)
27 #define NRD_ROS_MEMCNTRL_SIZE UL(0x10000000)
30 #define NRD_ROS_SYSTEM_PERIPH_BASE UL(0x0C000000)
31 #define NRD_ROS_SYSTEM_PERIPH_SIZE UL(0x02000000)
34 #define NRD_ROS_PLATFORM_PERIPH_BASE UL(0x0E000000)
35 #define NRD_ROS_PLATFORM_PERIPH_SIZE UL(0x02000000)
38 #define NRD_ROS_SMC0_BASE UL(0x08000000)
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H A Dnrd_css_def2.h18 #define NRD_CSS_SECURE_ROM_BASE UL(0x00000000)
24 #define NRD_CSS_NS_SRAM_BASE UL(0x06000000)
27 #define NRD_CSS_SEC_UART_BASE UL(0x2A410000)
28 #define NRD_CSS_NSEC_UART_BASE UL(0x2A400000)
29 #define NRD_CSS_UART_SIZE UL(0x10000)
32 #define NRD_CSS_PERIPH_BASE UL(0x20000000)
33 #define NRD_CSS_PERIPH_SIZE UL(0x20000000)
36 #define NRD_CSS_NS_RAM_ERR_REC_BASE UL(0x2A4C0000)
39 #define NRD_CSS_SECURE_WDOG_BASE UL(0x2A480000)
42 #define NRD_CSS_AP_SCP_S_MHU_BASE UL(0x2A920000)
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H A Dnrd_plat_arm_def2.h102 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
103 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
105 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
106 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
131 # define PLATFORM_STACK_SIZE UL(0x1000)
133 # define PLATFORM_STACK_SIZE UL(0x440)
137 # define PLATFORM_STACK_SIZE UL(0x1000)
139 # define PLATFORM_STACK_SIZE UL(0x400)
142 # define PLATFORM_STACK_SIZE UL(0x400)
145 # define PLATFORM_STACK_SIZE UL(0x500)
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/rk3399_ARM-atf/plat/arm/board/juno/
H A Djuno_def.h27 #define BL1_ROM_BYPASS_OFFSET UL(0x03EC0000)
29 #define EMMC_BASE UL(0x0c000000)
30 #define EMMC_SIZE UL(0x04000000)
32 #define PSRAM_BASE UL(0x14000000)
33 #define PSRAM_SIZE UL(0x02000000)
62 #define TRNG_BASE UL(0x7FE60000)
64 #define TRNG_STATUS UL(0x10)
65 #define TRNG_INTMASK UL(0x14)
66 #define TRNG_CONFIG UL(0x18)
67 #define TRNG_CONTROL UL(0x1C)
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/rk3399_ARM-atf/plat/arm/board/fvp/include/
H A Dplatform_def.h46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024))
48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000)
49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */
51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000)
52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
58 #define PLAT_ARM_RMM_PAYLOAD_SIZE UL(0x600000) /* 2 * 3MB */
78 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
81 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
144 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000))
164 #define PLAT_ARM_TB_FW_CONFIG_SIZE UL(0x0)
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/rk3399_ARM-atf/include/drivers/arm/
H A Dcci.h13 #define SLAVE_IFACE6_OFFSET UL(0x7000)
14 #define SLAVE_IFACE5_OFFSET UL(0x6000)
15 #define SLAVE_IFACE4_OFFSET UL(0x5000)
16 #define SLAVE_IFACE3_OFFSET UL(0x4000)
17 #define SLAVE_IFACE2_OFFSET UL(0x3000)
18 #define SLAVE_IFACE1_OFFSET UL(0x2000)
19 #define SLAVE_IFACE0_OFFSET UL(0x1000)
21 (UL(0x1000) * (index)))
24 #define EVENT_SELECT7_OFFSET UL(0x80000)
25 #define EVENT_SELECT6_OFFSET UL(0x70000)
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/rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/include/
H A Dplatform_def.h36 #define BL2_BASE UL(0x34078000)
37 #define BL2_LIMIT UL(0x34100000)
40 #define BL31_BASE UL(0x34200000)
41 #define BL31_LIMIT UL(0x34300000)
44 #define BL33_BASE UL(0x34500000)
45 #define BL33_LIMIT UL(0x345FF000)
59 #define UART_BASE UL(0x401C8000)
64 #define S32G_USDHC_BASE UL(0x402F0000)
66 #define S32G_FIP_BASE UL(0x34100000)
67 #define S32G_FIP_SIZE UL(0x100000)
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H A Ds32cc-ncore.h12 #define NCORE_BASE_ADDR UL(0x50400000)
23 #define NCORE_DIRU(N) (NCORE_BASE_ADDR + UL(0x80000) + ((N) * UL(0x1000)))
26 #define NCORE_DIRUSFE(N) (NCORE_DIRU(N) + UL(0x10))
30 #define NCORE_DIRUCASE(N) (NCORE_DIRU(N) + UL(0x40))
34 #define NCORE_DIRUSFMC(N) (NCORE_DIRU(N) + UL(0x80))
39 #define NCORE_DIRUSFMA(N) (NCORE_DIRU(N) + UL(0x84))
48 #define NCORE_CAIU(N) (NCORE_BASE_ADDR + ((N) * UL(0x1000)))
52 #define NCORE_CAIUTC_OFF UL(0x0)
59 #define NCORE_CAIUID(n) (NCORE_CAIU(n) + UL(0xFFC))
66 #define NCORE_CSR (NCORE_BASE_ADDR + UL(0xFF000))
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/rk3399_ARM-atf/plat/arm/board/morello/include/
H A Dplatform_def.h39 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000))
70 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000)
76 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000)
86 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
87 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xE000)
98 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000)
100 # define PLAT_ARM_MAX_BL2_SIZE UL(0x14000)
103 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
139 # define PLATFORM_STACK_SIZE UL(0x1000)
141 # define PLATFORM_STACK_SIZE UL(0x440)
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