Lines Matching refs:UL

13 #define RCAR_DOMAIN			UL(0x0)
15 #define RCAR_TRUSTED_SRAM_BASE		UL(0x46400000)
16 #define RCAR_TRUSTED_SRAM_SIZE		UL(0x00022000)
19 #define RCAR_SHARED_MEM_SIZE		UL(0x00001000)
20 #define	RCAR_BL31_CRASH_BASE		(RCAR_TRUSTED_SRAM_BASE + UL(0x3F000))
21 #define RCAR_BL31_CRASH_SIZE		UL(0x00001000)
22 #define DEVICE_RCAR_BASE		UL(0xE6000000)
23 #define DEVICE_RCAR_SIZE		UL(0x00300000)
24 #define DEVICE_SRAM_BASE		UL(0xE6342000)
25 #define DEVICE_SRAM_SIZE		UL(0x00002000)
27 #define DEVICE_SRAM_DATA_SIZE		UL(0x00000100)
29 #define DEVICE_SRAM_STACK_SIZE		(UL(0x00001000) - DEVICE_SRAM_DATA_SIZE)
30 #define DEVICE_RCAR_BASE2		UL(0xE6370000)
31 #define DEVICE_RCAR_SIZE2		UL(0x19C90000)
34 #define MBOX_SIZE			UL(0x200)
38 					RCAR_SHARED_MEM_SIZE - UL(0x100))
53 #define CCI500_BASE			UL(0xF1200000)
61 #define APSREG_BASE			UL(0xE6280000)
62 #define APSREG_CCI500_AUX		(APSREG_BASE + UL(0x9010))
63 #define APSREG_P_CCI500_AUX		(APSREG_BASE + UL(0x29010))
70 #define PLAT_ARM_GICD_BASE		UL(0xF1000000)
71 #define PLAT_ARM_GICR_BASE		UL(0xF1060000)
83 #define RCAR_CNTC_BASE			UL(0xE6080000)
95 #define RCAR_APMU_BASE			(UL(0xE6170000) + (RCAR_DOMAIN * UL(0x1000)))
110 #define RCAR_SRESCR			(UL(0xE6160018) + (RCAR_DOMAIN * UL(0x4000)))
113 #define RCAR_PRR			UL(0xFFF00044)
127 #define DBSC4_REG_BASE				UL(0xE6790000)
128 #define DBSC4_REG_DBSYSCNT0			(DBSC4_REG_BASE + UL(0x0100))
129 #define DBSC4_REG_DBACEN			(DBSC4_REG_BASE + UL(0x0200))
130 #define DBSC4_REG_DBRFEN			(DBSC4_REG_BASE + UL(0x0204))
131 #define DBSC4_REG_DBCMD				(DBSC4_REG_BASE + UL(0x0208))
132 #define DBSC4_REG_DBWAIT			(DBSC4_REG_BASE + UL(0x0210))
133 #define DBSC4_REG_DBCALCNF			(DBSC4_REG_BASE + UL(0x0424))
134 #define DBSC4_REG_DBDFIPMSTRCNF			(DBSC4_REG_BASE + UL(0x0520))
135 #define DBSC4_REG_DBCAM0CTRL0			(DBSC4_REG_BASE + UL(0x0940))
136 #define DBSC4_REG_DBCAM0STAT0			(DBSC4_REG_BASE + UL(0x0980))