Lines Matching refs:UL
59 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */
65 #define NSRAM_BASE UL(0x2e000000)
66 #define NSRAM_SIZE UL(0x00008000) /* 32KB */
93 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
100 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
101 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
102 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000)
104 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
105 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
106 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0)
116 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000)
118 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000)
211 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
213 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000)
222 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x20000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
224 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
226 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
229 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
241 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000)
251 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000)
259 # define PLATFORM_STACK_SIZE UL(0x1000)
261 # define PLATFORM_STACK_SIZE UL(0x440)
265 # define PLATFORM_STACK_SIZE UL(0x1000)
267 # define PLATFORM_STACK_SIZE UL(0x400)
270 # define PLATFORM_STACK_SIZE UL(0x400)
273 # define PLATFORM_STACK_SIZE UL(0x800)
275 # define PLATFORM_STACK_SIZE UL(0x400)
278 # define PLATFORM_STACK_SIZE UL(0x440)
285 #define PLAT_ARM_CCI_BASE UL(0x2c090000)
293 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000)
314 #define PLAT_ARM_GICD_BASE UL(0x2c010000)
315 #define PLAT_ARM_GICC_BASE UL(0x2c02f000)
316 #define PLAT_ARM_GICH_BASE UL(0x2c04f000)
317 #define PLAT_ARM_GICV_BASE UL(0x2c06f000)
320 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000)
336 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80))
383 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000)
403 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x200)
405 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400)