Lines Matching refs:UL

13 #define RCAR_DOMAIN			UL(0x0)
15 #define RCAR_TRUSTED_SRAM_BASE		UL(0x8C200000) /* DRAM */
16 #define RCAR_TRUSTED_SRAM_SIZE		UL(0x00040000) /* 256kB */
19 #define RCAR_SHARED_MEM_SIZE		UL(0x00002000) /* 8kB */
21 #define RCAR_BL31_CRASH_SIZE		UL(0x00001000)
22 #define DEVICE_RCAR_BASE1		UL(0x10000000)
23 #define DEVICE_RCAR_SIZE1		UL(0x30000000)
24 #define DEVICE_RCAR_BASE2		UL(0xC0000000)
25 #define DEVICE_RCAR_SIZE2		UL(0x00C00000)
26 #define DEVICE_SRAM_BASE		UL(0xE9042000)
27 #define DEVICE_SRAM_SIZE		UL(0x00002000)
29 #define DEVICE_SRAM_DATA_SIZE		UL(0x00000100)
31 #define DEVICE_SRAM_STACK_SIZE		(UL(0x00001000) - DEVICE_SRAM_DATA_SIZE)
32 #define DEVICE_RCAR_BASE3		UL(0xE5000000)
33 #define DEVICE_RCAR_SIZE3		UL(0x1B000000)
36 #define MBOX_SIZE			UL(0x800) /* 2kB: 32 cores */
38 #define PARAMS_BASE			(RCAR_TRUSTED_SRAM_BASE - UL(0x100000))
39 #define PARAMS_SIZE			UL(0x8000) /* 32kB */
40 #define BOOT_KIND_BASE			(PARAMS_BASE + UL(0x1700))
56 #define CCI500_BASE			UL(0xF1200000)
63 #define PLAT_ARM_GICD_BASE		UL(0x39000000) /* GICD base address for View 1 */
64 #define PLAT_ARM_GICR_BASE		UL(0x38080000)
83 #define RCAR_CNTC_BASE			UL(0x1C000000)
87 #define RCAR_CONV_MICROSEC		UL(1000000)
104 #define RCAR_SCMI_CHANNEL_MMU_BASE	UL(0xC1060000) /* align 4kB */
105 #define RCAR_SCMI_CHANNEL_SIZE		UL(0x00001000) /* align 4kB (SCP FW defines 0x100) */
106 #define RCAR_SCMI_CHANNEL_BASE		UL(0xC1060E00) /* for A2P PSCI Command (SCP FW defines) */
108 #define MFIS_SCP_COMMON_BASE            UL(0x189E1000)
109 #define MFIS_MFISWACNTR_SCP             (MFIS_SCP_COMMON_BASE + UL(0x00000904))
110 #define MFISWACNTR_SCP_CODEVALUE_SET    UL(0xACC00000)
111 #define MFISWACNTR_SCP_REGISTERADDRESS_MASK	UL(0x000FFFFF)
113 #define RCAR_SCMI_MFIS_ADDR		UL(0x18840004)