Lines Matching refs:UL
11 #define MORELLO_NS_SRAM_BASE UL(0x06000000)
12 #define MORELLO_NS_SRAM_SIZE UL(0x00010000)
44 #define MORELLO_PLATFORM_INFO_BASE UL(0x06000000)
47 #define MORELLO_DMC0_MEMC_STATUS_REG UL(0x4E000000)
48 #define MORELLO_DMC1_MEMC_STATUS_REG UL(0x4E100000)
53 #define MORELLO_DMC0_MEMC_CMD_REG UL(0x4E000008)
54 #define MORELLO_DMC1_MEMC_CMD_REG UL(0x4E100008)
57 #define MORELLO_DMC0_CAP_CTRL_REG UL(0x4E000D00)
58 #define MORELLO_DMC1_CAP_CTRL_REG UL(0x4E100D00)
61 #define MORELLO_DMC0_TAG_CACHE_CTL UL(0x4E000D04)
62 #define MORELLO_DMC1_TAG_CACHE_CTL UL(0x4E100D04)
65 #define MORELLO_DMC0_TAG_CACHE_CFG UL(0x4E000D08)
66 #define MORELLO_DMC1_TAG_CACHE_CFG UL(0x4E100D08)
69 #define MORELLO_DMC0_MEM_ACCESS_CTL UL(0x4E000D0C)
70 #define MORELLO_DMC1_MEM_ACCESS_CTL UL(0x4E100D0C)
75 #define MORELLO_DMC0_MEM_ADDR_CTL UL(0x4E000D10)
76 #define MORELLO_DMC1_MEM_ADDR_CTL UL(0x4E100D10)
79 #define MORELLO_DMC0_MEM_ADDR_CTL2 UL(0x4E000D14)
80 #define MORELLO_DMC1_MEM_ADDR_CTL2 UL(0x4E100D14)
83 #define MORELLO_DMC0_SPL_CTL_REG UL(0x4E000D18)
84 #define MORELLO_DMC1_SPL_CTL_REG UL(0x4E100D18)
87 #define MORELLO_DMC0_ERR0CTLR0_REG UL(0x4E000708)
88 #define MORELLO_DMC1_ERR0CTLR0_REG UL(0x4E100708)
94 #define MORELLO_DMC0_ERR2STATUS_REG UL(0x4E000790)
95 #define MORELLO_DMC1_ERR2STATUS_REG UL(0x4E100790)