1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 58 #define PLAT_ARM_RMM_PAYLOAD_SIZE UL(0x600000) /* 2 * 3MB */ 59 60 /* Protected physical address size */ 61 #define PLAT_ARM_PPS (SZ_1T) 62 #endif /* ENABLE_RME */ 63 64 /* 65 * Max size of SPMC is 16MB for fvp. With SPMD enabled this value corresponds to 66 * max size of BL32 image. 67 */ 68 #if defined(SPD_spmd) 69 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 70 #define PLAT_ARM_SPMC_SIZE SZ_16M 71 #endif 72 73 /* Virtual address used by dynamic mem_protect for chunk_base */ 74 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 75 76 /* No SCP in FVP */ 77 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 78 79 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 80 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 81 82 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 83 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 84 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 85 86 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 87 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 88 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 89 90 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 91 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 92 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 93 94 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 95 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 96 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 97 98 /* 99 * On the FVP platform when using the EL3 SPMC implementation allocate the 100 * datastore for tracking shared memory descriptors in the TZC DRAM section 101 * to ensure sufficient storage can be allocated. 102 * Provide an implementation of the accessor method to allow the datastore 103 * details to be retrieved by the SPMC. 104 * The SPMC will take care of initializing the memory region. 105 */ 106 107 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 108 109 /* Define memory configuration for device tree files. */ 110 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 111 112 #if SPMC_AT_EL3 113 114 /* 115 * Number of Secure Partitions supported. 116 * SPMC at EL3, uses this count to configure the maximum number of supported 117 * secure partitions. 118 */ 119 #define SECURE_PARTITION_COUNT 1 120 121 /* 122 * Number of Normal World Partitions supported. 123 * SPMC at EL3, uses this count to configure the maximum number of supported 124 * NWd partitions. 125 */ 126 #define NS_PARTITION_COUNT 1 127 128 /* 129 * Number of Logical Partitions supported. 130 * SPMC at EL3, uses this count to configure the maximum number of supported 131 * logical partitions. 132 */ 133 #define MAX_EL3_LP_DESCS_COUNT 1 134 135 #endif /* SPMC_AT_EL3 */ 136 137 /* 138 * Load address of BL33 for this platform port 139 */ 140 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 141 142 #if TRANSFER_LIST 143 144 /* Define maximum size of sp manifest file. */ 145 #if defined(SPD_spmd) 146 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE SZ_4K 147 #else 148 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE UL(0x0) 149 #endif 150 151 /* 152 * PLAT_ARM_FW_HANDOFF_SIZE should be page-aligned to ensure proper xlat mapping. 153 * If it is not, generating the page table mapping for FW_HANDOFF will fail. 154 * Because PLAT_ARM_EVENT_LOG_MAX_SIZE is not guaranteed to be aligned, 155 * PLAT_ARM_FW_HANDOFF_SIZE must be explicitly aligned. 156 */ 157 #define PLAT_ARM_FW_HANDOFF_SIZE ((((PLAT_ARM_HW_CONFIG_SIZE + \ 158 PLAT_ARM_EVENT_LOG_MAX_SIZE + \ 159 PLAT_ARM_SPMC_SP_MANIFEST_SIZE) + \ 160 PAGE_SIZE_MASK) >> \ 161 PAGE_SIZE_SHIFT) << PAGE_SIZE_SHIFT) 162 163 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 164 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 165 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 166 167 #if RESET_TO_BL31 168 #define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET 169 #endif 170 171 #else 172 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 173 #endif 174 175 /* 176 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 177 * plat_arm_mmap array defined for each BL stage. 178 */ 179 #if defined(IMAGE_BL31) 180 # if SPM_MM 181 # define PLAT_ARM_MMAP_ENTRIES 10 182 # define MAX_XLAT_TABLES 9 183 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 184 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 185 # elif SPMC_AT_EL3 186 # define PLAT_ARM_MMAP_ENTRIES 13 187 # define MAX_XLAT_TABLES 11 188 # define PLAT_SP_IMAGE_MMAP_REGIONS 31 189 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 13 190 # else 191 # define PLAT_ARM_MMAP_ENTRIES 9 192 # if USE_DEBUGFS 193 # if ENABLE_RME 194 # define MAX_XLAT_TABLES 9 195 # else 196 # define MAX_XLAT_TABLES 8 197 # endif 198 # else 199 # if ENABLE_RME 200 # define MAX_XLAT_TABLES 8 201 # elif DRTM_SUPPORT 202 # define MAX_XLAT_TABLES 8 203 # else 204 # define MAX_XLAT_TABLES 7 205 # endif 206 # endif 207 # endif 208 #elif defined(IMAGE_BL32) 209 # if SPMC_AT_EL3 210 # define PLAT_ARM_MMAP_ENTRIES 270 211 # define MAX_XLAT_TABLES 10 212 # else 213 # define PLAT_ARM_MMAP_ENTRIES 9 214 # define MAX_XLAT_TABLES 6 215 # endif 216 #elif !USE_ROMLIB 217 # if defined(IMAGE_BL2) && (ENABLE_RME || SPMC_AT_EL3) 218 # define PLAT_ARM_MMAP_ENTRIES 12 219 # define MAX_XLAT_TABLES 6 220 # else 221 # define PLAT_ARM_MMAP_ENTRIES 12 222 # define MAX_XLAT_TABLES 5 223 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 224 #else 225 # define PLAT_ARM_MMAP_ENTRIES 12 226 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 227 defined(IMAGE_BL2) && MEASURED_BOOT 228 # define MAX_XLAT_TABLES 7 229 # else 230 # define MAX_XLAT_TABLES 6 231 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 232 #endif 233 234 /* 235 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 236 * plus a little space for growth. 237 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 238 * area. 239 */ 240 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \ 241 FVP_TRUSTED_SRAM_SIZE == 512 242 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xD000) 243 #else 244 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 245 #endif 246 247 /* 248 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 249 */ 250 251 #if USE_ROMLIB 252 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 253 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 254 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 255 #else 256 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 257 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 258 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 259 #endif 260 261 /* 262 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 263 * Maximum size of BL2 increases as Trusted SRAM size increases. 264 */ 265 #if (defined(TF_MBEDTLS_KEY_ALG_ID) && \ 266 (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA)) || \ 267 (TRUSTED_BOARD_BOOT && COT_DESC_IN_DTB) 268 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 269 (2 * PAGE_SIZE) - \ 270 FVP_BL2_ROMLIB_OPTIMIZATION) 271 #elif TRUSTED_BOARD_BOOT || MEASURED_BOOT 272 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 273 (3 * PAGE_SIZE) - \ 274 FVP_BL2_ROMLIB_OPTIMIZATION) 275 #elif ARM_BL31_IN_DRAM 276 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 277 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 278 #else 279 /** 280 * Default to just under half of SRAM to ensure there's enough room for really 281 * large BL31 build configurations when using the default SRAM size (256 Kb). 282 */ 283 #define PLAT_ARM_MAX_BL2_SIZE \ 284 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 285 FVP_BL2_ROMLIB_OPTIMIZATION) 286 #endif 287 288 #if RESET_TO_BL31 289 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 290 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 291 ARM_SHARED_RAM_SIZE - \ 292 ARM_L0_GPT_SIZE) 293 #else 294 /* 295 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 296 * calculated using the current BL31 PROGBITS debug size plus the sizes of 297 * BL2 and BL1-RW. 298 * Size of the BL31 PROGBITS increases as the SRAM size increases. 299 */ 300 #if TRANSFER_LIST 301 #define PLAT_ARM_MAX_BL31_SIZE \ 302 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 303 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 304 #else 305 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 306 ARM_SHARED_RAM_SIZE - \ 307 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 308 #endif /* TRANSFER_LIST */ 309 #endif /* RESET_TO_BL31 */ 310 311 #ifndef __aarch64__ 312 #if RESET_TO_SP_MIN 313 /* Size of Trusted SRAM - the first 4KB of shared memory */ 314 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 315 ARM_SHARED_RAM_SIZE) 316 #else 317 /* 318 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 319 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 320 * BL2 and BL1-RW 321 */ 322 #if TRANSFER_LIST 323 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 324 ARM_SHARED_RAM_SIZE - \ 325 PLAT_ARM_FW_HANDOFF_SIZE) 326 #else 327 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 328 ARM_SHARED_RAM_SIZE - \ 329 ARM_FW_CONFIGS_SIZE) 330 #endif /* TRANSFER_LIST */ 331 #endif /* RESET_TO_SP_MIN */ 332 #endif 333 334 /* 335 * Size of cacheable stacks 336 */ 337 #if defined(IMAGE_BL1) 338 # if CRYPTO_SUPPORT 339 # define PLATFORM_STACK_SIZE UL(0x1000) 340 # else 341 # define PLATFORM_STACK_SIZE UL(0x500) 342 # endif /* CRYPTO_SUPPORT */ 343 #elif defined(IMAGE_BL2) 344 # if CRYPTO_SUPPORT 345 # define PLATFORM_STACK_SIZE UL(0x1000) 346 # else 347 # define PLATFORM_STACK_SIZE UL(0x600) 348 # endif /* CRYPTO_SUPPORT */ 349 #elif defined(IMAGE_BL2U) 350 # define PLATFORM_STACK_SIZE UL(0x400) 351 #elif defined(IMAGE_BL31) 352 # if DRTM_SUPPORT 353 # define PLATFORM_STACK_SIZE UL(0x1000) 354 # else 355 # define PLATFORM_STACK_SIZE UL(0x800) 356 # endif /* DRTM_SUPPORT */ 357 #elif defined(IMAGE_BL32) 358 # if SPMC_AT_EL3 359 # define PLATFORM_STACK_SIZE UL(0x1000) 360 # else 361 # define PLATFORM_STACK_SIZE UL(0x440) 362 # endif /* SPMC_AT_EL3 */ 363 #elif defined(IMAGE_RMM) 364 # define PLATFORM_STACK_SIZE UL(0x440) 365 #endif 366 367 #define MAX_IO_DEVICES 3 368 #define MAX_IO_HANDLES 4 369 370 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 371 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 372 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 373 374 #if ARM_GPT_SUPPORT && IMAGE_BL1 375 /* 376 * Offset of the FIP in the GPT image. BL1 component uses this option 377 * as it does not load the partition table to get the FIP base 378 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 379 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 380 */ 381 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 382 #endif /* ARM_GPT_SUPPORT */ 383 384 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 385 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 386 387 /* 388 * PL011 related constants 389 */ 390 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 391 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 392 393 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 394 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 395 396 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 397 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 398 399 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 400 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 401 402 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 403 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 404 405 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 406 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 407 408 /* CCI related constants */ 409 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 410 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 411 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 412 413 /* CCI-500/CCI-550 on Base platform */ 414 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 415 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 416 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 417 418 /* CCN related constants. Only CCN 502 is currently supported */ 419 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 420 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 421 422 /* System timer related constants */ 423 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 424 425 /* Mailbox base address */ 426 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 427 428 /* PCIe memory region 1 (Base Platform RevC only) */ 429 #define PLAT_ARM_PCI_MEM_1_BASE (ULL(0x50000000)) 430 #define PLAT_ARM_PCI_MEM_1_SIZE (SZ_256M) /* 256MB */ 431 432 /* 433 * PCIe memory region 2 (Base Platform RevC only) 434 * The full size of the second PCI memory region is 256GB 435 * but for now we only allocate the L1 GPTs for the first 3GB. 436 */ 437 #define PLAT_ARM_PCI_MEM_2_BASE (ULL(0x4000000000)) 438 #define PLAT_ARM_PCI_MEM_2_SIZE (3 * SZ_1G) /* 3GB */ 439 440 /* TrustZone controller related constants 441 * 442 * Currently only filters 0 and 2 are connected on Base FVP. 443 * Filter 0 : CPU clusters (no access to DRAM by default) 444 * Filter 1 : not connected 445 * Filter 2 : LCDs (access to VRAM allowed by default) 446 * Filter 3 : not connected 447 * Programming unconnected filters will have no effect at the 448 * moment. These filter could, however, be connected in future. 449 * So care should be taken not to configure the unused filters. 450 * 451 * Allow only non-secure access to all DRAM to supported devices. 452 * Give access to the CPUs and Virtio. Some devices 453 * would normally use the default ID so allow that too. 454 */ 455 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 456 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 457 458 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 459 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 460 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 461 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 462 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 463 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 464 465 /* 466 * GIC related constants to cater for both GICv2 and GICv3 instances of an 467 * FVP. They could be overridden at runtime in case the FVP implements the 468 * legacy VE memory map. 469 */ 470 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 471 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 472 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 473 474 /* 475 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 476 * terminology. On a GICv2 system or mode, the lists will be merged and treated 477 * as Group 0 interrupts. 478 */ 479 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 480 ARM_G1S_IRQ_PROPS(grp), \ 481 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 482 GIC_INTR_CFG_LEVEL), \ 483 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 484 GIC_INTR_CFG_LEVEL) 485 486 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 487 488 #if SDEI_IN_FCONF 489 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 490 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 491 #else 492 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 493 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 494 ARM_SDEI_PRIVATE_EVENTS, \ 495 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 496 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 497 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 498 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 499 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 500 #else 501 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 502 #endif 503 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 504 #endif 505 506 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SPM_BUF_BASE + \ 507 PLAT_SPM_BUF_SIZE) 508 509 #define PLAT_SP_PRI 0x20 510 511 /* 512 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 513 */ 514 #ifdef __aarch64__ 515 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 516 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 517 #else 518 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 519 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 520 #endif 521 522 /* 523 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 524 * TODO: calculate maximum EventLog size using the calculation: 525 * Maximum size of Event Log * Number of images 526 */ 527 #if (defined(SPD_spmd)) || (ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed))) 528 /* 529 * Account for additional measurements of secure partitions and SPM. 530 * Also, account for OP-TEE running with maximum number of SPs. 531 */ 532 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 533 #elif defined(IMAGE_BL1) && TRANSFER_LIST 534 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x200) 535 #else 536 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 537 #endif 538 539 /* 540 * Maximum size of Event Log buffer used for DRTM 541 */ 542 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 543 544 /* 545 * Number of MMAP entries used by DRTM implementation 546 */ 547 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 548 549 #endif /* PLATFORM_DEF_H */ 550