Lines Matching refs:UL
46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024))
48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000)
49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */
51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000)
52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
58 #define PLAT_ARM_RMM_PAYLOAD_SIZE UL(0x600000) /* 2 * 3MB */
78 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
81 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
144 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000))
164 #define PLAT_ARM_TB_FW_CONFIG_SIZE UL(0x0)
169 #define PLAT_ARM_SPMC_SP_MANIFEST_SIZE UL(0x0)
170 #define PLAT_ARM_TB_FW_CONFIG_SIZE UL(0x0)
266 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xD000)
268 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
276 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
277 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
278 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000)
280 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
281 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
282 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0)
301 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION)
363 # define PLATFORM_STACK_SIZE UL(0x1000)
365 # define PLATFORM_STACK_SIZE UL(0x500)
369 # define PLATFORM_STACK_SIZE UL(0x1000)
371 # define PLATFORM_STACK_SIZE UL(0x600)
374 # define PLATFORM_STACK_SIZE UL(0x400)
377 # define PLATFORM_STACK_SIZE UL(0x1000)
379 # define PLATFORM_STACK_SIZE UL(0x800)
383 # define PLATFORM_STACK_SIZE UL(0x1000)
385 # define PLATFORM_STACK_SIZE UL(0x440)
388 # define PLATFORM_STACK_SIZE UL(0x440)
429 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000)
430 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000)
433 #define PLAT_FVP_CCI400_BASE UL(0x2c090000)
438 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000)
443 #define PLAT_ARM_CCN_BASE UL(0x2e000000)
479 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000)
568 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300)