Lines Matching refs:UL
39 #define FLASH1_BASE UL(0x0c000000)
40 #define FLASH1_SIZE UL(0x04000000)
42 #define PSRAM_BASE UL(0x14000000)
43 #define PSRAM_SIZE UL(0x04000000)
45 #define VRAM_BASE UL(0x18000000)
46 #define VRAM_SIZE UL(0x02000000)
49 #define DEVICE0_BASE UL(0x20000000)
50 #define DEVICE0_SIZE UL(0x0c200000)
56 #define CCN_BASE UL(0x2e000000)
57 #define CCN_SIZE UL(0x1000000)
77 #define DEVICE2_BASE UL(0x7fe00000)
78 #define DEVICE2_SIZE UL(0x00200000)
80 #define PCIE_EXP_BASE UL(0x40000000)
81 #define TZRNG_BASE UL(0x7fe60000)
84 #define TRUSTED_NVCTR_BASE UL(0x7fe70000)
85 #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000))
86 #define TFW_NVCTR_SIZE UL(4)
87 #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004))
88 #define NTFW_CTR_SIZE UL(4)
91 #define SOC_KEYS_BASE UL(0x7fe80000)
92 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000))
93 #define TZ_PUB_KEY_HASH_SIZE UL(32)
94 #define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020))
95 #define HU_KEY_SIZE UL(16)
96 #define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044))
97 #define END_KEY_SIZE UL(32)
116 #define PWRC_BASE UL(0x1c100000)
129 #define NSRAM_BASE UL(0x2e000000)
130 #define NSRAM_SIZE UL(0x10000)
135 #define CCN_BASE UL(0x2e000000)
136 #define CCN_SIZE UL(0x1000000)
141 #define VE_GICD_BASE UL(0x2c001000)
142 #define VE_GICC_BASE UL(0x2c002000)
143 #define VE_GICH_BASE UL(0x2c004000)
144 #define VE_GICV_BASE UL(0x2c006000)
147 #define BASE_GICD_BASE UL(0x2f000000)
148 #define BASE_GICD_SIZE UL(0x10000)
149 #define BASE_GICR_BASE UL(0x2f100000)
151 #define BASE_IWB_BASE UL(0x2f000000)
152 #define BASE_IRS_BASE UL(0x2f1c0000)
156 #define BASE_GICR_SIZE UL(0x40000)
158 #define BASE_GICR_SIZE UL(0x20000)
161 #define BASE_GICC_BASE UL(0x2c000000)
162 #define BASE_GICH_BASE UL(0x2c010000)
163 #define BASE_GICV_BASE UL(0x2c02f000)