xref: /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/include/s32cc-ncore.h (revision 75b0d5756fdbe122c4692f50153cc31b9843f5a5)
1*5071f7c7SGhennadi Procopciuc /*
2*5071f7c7SGhennadi Procopciuc  * Copyright 2019-2021, 2024 NXP
3*5071f7c7SGhennadi Procopciuc  *
4*5071f7c7SGhennadi Procopciuc  * SPDX-License-Identifier: BSD-3-Clause
5*5071f7c7SGhennadi Procopciuc  */
6*5071f7c7SGhennadi Procopciuc 
7*5071f7c7SGhennadi Procopciuc #ifndef S32G2_NCORE_H
8*5071f7c7SGhennadi Procopciuc #define S32G2_NCORE_H
9*5071f7c7SGhennadi Procopciuc 
10*5071f7c7SGhennadi Procopciuc #include <stdbool.h>
11*5071f7c7SGhennadi Procopciuc 
12*5071f7c7SGhennadi Procopciuc #define NCORE_BASE_ADDR			UL(0x50400000)
13*5071f7c7SGhennadi Procopciuc 
14*5071f7c7SGhennadi Procopciuc #define A53_CLUSTER0_CAIU		U(0)
15*5071f7c7SGhennadi Procopciuc #define A53_CLUSTER1_CAIU		U(1)
16*5071f7c7SGhennadi Procopciuc 
17*5071f7c7SGhennadi Procopciuc /**
18*5071f7c7SGhennadi Procopciuc  * Directory Unit Registers
19*5071f7c7SGhennadi Procopciuc  *
20*5071f7c7SGhennadi Procopciuc  * The directory provides a point of serialization for establishing transaction
21*5071f7c7SGhennadi Procopciuc  * ordering and sequences coherence operations and memory accesses.
22*5071f7c7SGhennadi Procopciuc  */
23*5071f7c7SGhennadi Procopciuc #define NCORE_DIRU(N)			(NCORE_BASE_ADDR + UL(0x80000) + ((N) * UL(0x1000)))
24*5071f7c7SGhennadi Procopciuc 
25*5071f7c7SGhennadi Procopciuc /* DIRU Snoop Filtering Enable */
26*5071f7c7SGhennadi Procopciuc #define NCORE_DIRUSFE(N)		(NCORE_DIRU(N) + UL(0x10))
27*5071f7c7SGhennadi Procopciuc #define NCORE_DIRUSFE_SFEN(SF)		BIT_32(SF)
28*5071f7c7SGhennadi Procopciuc 
29*5071f7c7SGhennadi Procopciuc /* DIRU Caching Agent Snoop Enable */
30*5071f7c7SGhennadi Procopciuc #define NCORE_DIRUCASE(N)		(NCORE_DIRU(N) + UL(0x40))
31*5071f7c7SGhennadi Procopciuc #define NCORE_DIRUCASE_CASNPEN(CAIU)	BIT_32(CAIU)
32*5071f7c7SGhennadi Procopciuc 
33*5071f7c7SGhennadi Procopciuc /* DIRU Snoop Filter Maintenance Control */
34*5071f7c7SGhennadi Procopciuc #define NCORE_DIRUSFMC(N)		(NCORE_DIRU(N) + UL(0x80))
35*5071f7c7SGhennadi Procopciuc #define NCORE_DIRUSFMC_SFID(SF)		((SF) << 16U)
36*5071f7c7SGhennadi Procopciuc #define NCORE_DIRUSFMC_SFMNTOP_ALL	U(0x0)
37*5071f7c7SGhennadi Procopciuc 
38*5071f7c7SGhennadi Procopciuc /* DIRU Snoop Filter Maintenance Activity */
39*5071f7c7SGhennadi Procopciuc #define NCORE_DIRUSFMA(N)		(NCORE_DIRU(N) + UL(0x84))
40*5071f7c7SGhennadi Procopciuc #define NCORE_DIRUSFMA_MNTOPACTV	BIT_32(0)
41*5071f7c7SGhennadi Procopciuc 
42*5071f7c7SGhennadi Procopciuc /**
43*5071f7c7SGhennadi Procopciuc  * Coherent Agent Interface Unit Registers
44*5071f7c7SGhennadi Procopciuc  *
45*5071f7c7SGhennadi Procopciuc  * CAI provides a means for a fully-coherent agent to be connected to the Ncore.
46*5071f7c7SGhennadi Procopciuc  * The CAI behaves as a fully-coherent slave.
47*5071f7c7SGhennadi Procopciuc  */
48*5071f7c7SGhennadi Procopciuc #define NCORE_CAIU(N)			(NCORE_BASE_ADDR + ((N) * UL(0x1000)))
49*5071f7c7SGhennadi Procopciuc #define NCORE_CAIU0_BASE_ADDR		NCORE_BASE_ADDR
50*5071f7c7SGhennadi Procopciuc 
51*5071f7c7SGhennadi Procopciuc /* CAIU Transaction Control */
52*5071f7c7SGhennadi Procopciuc #define NCORE_CAIUTC_OFF		UL(0x0)
53*5071f7c7SGhennadi Procopciuc #define NCORE_CAIUTC_ISOLEN_SHIFT	U(1)
54*5071f7c7SGhennadi Procopciuc #define NCORE_CAIUTC_ISOLEN_MASK	BIT_32(NCORE_CAIUTC_ISOLEN_SHIFT)
55*5071f7c7SGhennadi Procopciuc 
56*5071f7c7SGhennadi Procopciuc #define NCORE_CAIUTC(N)			(NCORE_CAIU(N) + NCORE_CAIUTC_OFF)
57*5071f7c7SGhennadi Procopciuc 
58*5071f7c7SGhennadi Procopciuc /* CAIU Identification */
59*5071f7c7SGhennadi Procopciuc #define NCORE_CAIUID(n)			(NCORE_CAIU(n) + UL(0xFFC))
60*5071f7c7SGhennadi Procopciuc #define NCORE_CAIUID_TYPE		GENMASK_32(U(19), U(16))
61*5071f7c7SGhennadi Procopciuc #define NCORE_CAIUID_TYPE_ACE_DVM	U(0x0)
62*5071f7c7SGhennadi Procopciuc 
63*5071f7c7SGhennadi Procopciuc /**
64*5071f7c7SGhennadi Procopciuc  * Coherent Subsystem Registers
65*5071f7c7SGhennadi Procopciuc  */
66*5071f7c7SGhennadi Procopciuc #define NCORE_CSR			(NCORE_BASE_ADDR + UL(0xFF000))
67*5071f7c7SGhennadi Procopciuc 
68*5071f7c7SGhennadi Procopciuc /* Coherent Subsystem ACE DVM Snoop Enable */
69*5071f7c7SGhennadi Procopciuc #define NCORE_CSADSE			(NCORE_CSR + UL(0x40))
70*5071f7c7SGhennadi Procopciuc #define NCORE_CSADSE_DVMSNPEN(CAIU)	BIT_32(CAIU)
71*5071f7c7SGhennadi Procopciuc 
72*5071f7c7SGhennadi Procopciuc /* Coherent Subsystem Identification */
73*5071f7c7SGhennadi Procopciuc #define NCORE_CSID			(NCORE_CSR + UL(0xFFC))
74*5071f7c7SGhennadi Procopciuc #define NCORE_CSID_NUMSFS_SHIFT		U(18)
75*5071f7c7SGhennadi Procopciuc #define NCORE_CSID_NUMSFS_MASK		GENMASK_32(U(22), NCORE_CSID_NUMSFS_SHIFT)
76*5071f7c7SGhennadi Procopciuc #define NCORE_CSID_NUMSFS(CSIDR)	(((CSIDR) & NCORE_CSID_NUMSFS_MASK) \
77*5071f7c7SGhennadi Procopciuc 					  >> NCORE_CSID_NUMSFS_SHIFT)
78*5071f7c7SGhennadi Procopciuc 
79*5071f7c7SGhennadi Procopciuc /* Coherent Subsystem Unit Identification */
80*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID			(NCORE_CSR + UL(0xFF8))
81*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID_NUMCMIUS_SHIFT	U(24)
82*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID_NUMCMIUS_MASK	GENMASK_32(U(29), NCORE_CSUID_NUMCMIUS_SHIFT)
83*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID_NUMCMIUS(CSUIDR)	(((CSUIDR) & NCORE_CSUID_NUMCMIUS_MASK) \
84*5071f7c7SGhennadi Procopciuc 					 >> NCORE_CSUID_NUMCMIUS_SHIFT)
85*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID_NUMDIRUS_SHIFT	U(16)
86*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID_NUMDIRUS_MASK	GENMASK_32(U(21), NCORE_CSUID_NUMDIRUS_SHIFT)
87*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID_NUMDIRUS(CSUIDR)	(((CSUIDR) & NCORE_CSUID_NUMDIRUS_MASK) \
88*5071f7c7SGhennadi Procopciuc 					 >> NCORE_CSUID_NUMDIRUS_SHIFT)
89*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID_NUMNCBUS_SHIFT	U(8)
90*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID_NUMNCBUS_MASK	GENMASK_32(U(13), NCORE_CSUID_NUMNCBUS_SHIFT)
91*5071f7c7SGhennadi Procopciuc #define NCORE_CSUID_NUMNCBUS(CSUIDR)	(((CSUIDR) & NCORE_CSUID_NUMNCBUS_MASK) \
92*5071f7c7SGhennadi Procopciuc 					 >> NCORE_CSUID_NUMNCBUS_SHIFT)
93*5071f7c7SGhennadi Procopciuc 
94*5071f7c7SGhennadi Procopciuc #ifndef __ASSEMBLER__
95*5071f7c7SGhennadi Procopciuc void ncore_caiu_online(uint32_t caiu);
96*5071f7c7SGhennadi Procopciuc void ncore_caiu_offline(uint32_t caiu);
97*5071f7c7SGhennadi Procopciuc void ncore_init(void);
98*5071f7c7SGhennadi Procopciuc bool ncore_is_caiu_online(uint32_t caiu);
99*5071f7c7SGhennadi Procopciuc void ncore_disable_caiu_isolation(uint32_t caiu);
100*5071f7c7SGhennadi Procopciuc #endif /* __ASSEMBLER__ */
101*5071f7c7SGhennadi Procopciuc 
102*5071f7c7SGhennadi Procopciuc #endif /* S32G2_NCORE_H */
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