Home
last modified time | relevance | path

Searched refs:_parent (Results 1 – 25 of 113) sorted by relevance

12345

/OK3568_Linux_fs/kernel/drivers/clk/sprd/
H A Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
42 .hw.init = _fn(_name, _parent, \
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument
50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
54 #define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \ argument
56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
62 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
[all …]
H A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
80 .hw.init = _fn(_name, _parent, \
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument
108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
[all …]
H A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
30 .hw.init = _fn(_name, _parent, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
55 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
H A Ddiv.h38 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
45 .hw.init = _fn(_name, _parent, \
50 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument
52 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
55 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument
57 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
/OK3568_Linux_fs/kernel/drivers/clk/zte/
H A Dclk.h37 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
44 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
52 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
53 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
68 _parent, \
80 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
86 _parent, \
98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
107 _parent, \
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
H A Dclk-mt8167.c657 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
660 .parent_name = _parent, \
687 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
690 .parent_name = _parent, \
738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
741 .parent_name = _parent, \
747 #define GATE_TOP0_I(_id, _name, _parent, _shift) { \ argument
750 .parent_name = _parent, \
756 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
759 .parent_name = _parent, \
[all …]
H A Dclk-mt2701-aud.c18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
21 .parent_name = _parent, \
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
30 .parent_name = _parent, \
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
39 .parent_name = _parent, \
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
48 .parent_name = _parent, \
H A Dclk-mt7622-aud.c19 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
22 .parent_name = _parent, \
28 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
31 .parent_name = _parent, \
37 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
40 .parent_name = _parent, \
46 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
49 .parent_name = _parent, \
H A Dclk-mt8173.c622 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
625 .parent_name = _parent, \
661 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
664 .parent_name = _parent, \
670 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
673 .parent_name = _parent, \
737 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
740 .parent_name = _parent, \
768 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
771 .parent_name = _parent, \
[all …]
H A Dclk-mt8516.c467 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
470 .parent_name = _parent, \
527 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
530 .parent_name = _parent, \
536 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
539 .parent_name = _parent, \
545 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ argument
548 .parent_name = _parent, \
554 #define GATE_TOP3(_id, _name, _parent, _shift) { \ argument
557 .parent_name = _parent, \
[all …]
H A Dclk-mtk.h29 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
32 .parent = _parent, \
47 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
50 .parent_name = _parent, \
131 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ argument
134 .parent = _parent, \
190 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
193 .parent_name = _parent, \
H A Dclk-mt2712-mm.c33 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
36 .parent_name = _parent, \
42 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
45 .parent_name = _parent, \
51 #define GATE_MM2(_id, _name, _parent, _shift) { \ argument
54 .parent_name = _parent, \
H A Dclk-mt7622.c52 #define GATE_APMIXED(_id, _name, _parent, _shift) { \ argument
55 .parent_name = _parent, \
61 #define GATE_INFRA(_id, _name, _parent, _shift) { \ argument
64 .parent_name = _parent, \
70 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
73 .parent_name = _parent, \
79 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
82 .parent_name = _parent, \
88 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
91 .parent_name = _parent, \
[all …]
H A Dclk-mt6765.c485 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
488 .parent_name = _parent, \
494 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
497 .parent_name = _parent, \
503 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
506 .parent_name = _parent, \
561 #define GATE_IFR2(_id, _name, _parent, _shift) { \ argument
564 .parent_name = _parent, \
570 #define GATE_IFR3(_id, _name, _parent, _shift) { \ argument
573 .parent_name = _parent, \
[all …]
H A Dclk-mt8183.c756 #define GATE_TOP(_id, _name, _parent, _shift) \ argument
757 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \
790 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
791 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
794 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
795 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
798 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
799 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
802 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
803 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
[all …]
H A Dclk-mt8183-vdec.c26 #define GATE_VDEC0_I(_id, _name, _parent, _shift) \ argument
27 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
30 #define GATE_VDEC1_I(_id, _name, _parent, _shift) \ argument
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
H A Dclk-mt6779-vdec.c27 #define GATE_VDEC0_I(_id, _name, _parent, _shift) \ argument
28 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
30 #define GATE_VDEC1_I(_id, _name, _parent, _shift) \ argument
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
/OK3568_Linux_fs/kernel/drivers/clk/renesas/
H A Drenesas-cpg-mssr.h46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
47 DEF_TYPE(_name, _id, _type, .parent = _parent)
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
52 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
56 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
76 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
[all …]
H A Drcar-gen3-cpg.h34 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
35 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
47 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
48 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
54 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
55 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
/OK3568_Linux_fs/kernel/drivers/clk/actions/
H A Dowl-composite.h37 #define OWL_COMP_DIV(_struct, _name, _parent, \ argument
46 _parent, \
52 #define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ argument
60 _parent, \
66 #define OWL_COMP_FACTOR(_struct, _name, _parent, \ argument
75 _parent, \
81 #define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \ argument
91 _parent, \
97 #define OWL_COMP_PASS(_struct, _name, _parent, \ argument
105 _parent, \
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
25 _parent, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
37 _parent, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
49 _parent, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
65 _parent, \
H A Dccu_nm.h38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
55 _parent, \
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
79 _parent, \
85 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \ argument
105 _parent, \
112 _parent, _reg, \ argument
134 _parent, \
140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
152 _parent, \
H A Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
97 _parent, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
149 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
158 _parent, \
164 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
166 SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
/OK3568_Linux_fs/kernel/include/linux/
H A Dsh_clk.h117 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ argument
119 .parent = _parent, \
151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
153 .parent = _parent, \
188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
190 .parent = _parent, \
205 #define SH_CLK_FSIDIV(_reg, _parent) \ argument
208 .parent = _parent, \

12345