xref: /OK3568_Linux_fs/kernel/drivers/clk/mediatek/clk-mt8183-vdec.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2018 MediaTek Inc.
4*4882a593Smuzhiyun // Author: Weiyi Lu <weiyi.lu@mediatek.com>
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/platform_device.h>
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include "clk-mtk.h"
10*4882a593Smuzhiyun #include "clk-gate.h"
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <dt-bindings/clock/mt8183-clk.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun static const struct mtk_gate_regs vdec0_cg_regs = {
15*4882a593Smuzhiyun 	.set_ofs = 0x0,
16*4882a593Smuzhiyun 	.clr_ofs = 0x4,
17*4882a593Smuzhiyun 	.sta_ofs = 0x0,
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun static const struct mtk_gate_regs vdec1_cg_regs = {
21*4882a593Smuzhiyun 	.set_ofs = 0x8,
22*4882a593Smuzhiyun 	.clr_ofs = 0xc,
23*4882a593Smuzhiyun 	.sta_ofs = 0x8,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define GATE_VDEC0_I(_id, _name, _parent, _shift)		\
27*4882a593Smuzhiyun 	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift,	\
28*4882a593Smuzhiyun 		&mtk_clk_gate_ops_setclr_inv)
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define GATE_VDEC1_I(_id, _name, _parent, _shift)		\
31*4882a593Smuzhiyun 	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift,	\
32*4882a593Smuzhiyun 		&mtk_clk_gate_ops_setclr_inv)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static const struct mtk_gate vdec_clks[] = {
35*4882a593Smuzhiyun 	/* VDEC0 */
36*4882a593Smuzhiyun 	GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0),
37*4882a593Smuzhiyun 	/* VDEC1 */
38*4882a593Smuzhiyun 	GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
clk_mt8183_vdec_probe(struct platform_device * pdev)41*4882a593Smuzhiyun static int clk_mt8183_vdec_probe(struct platform_device *pdev)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	struct clk_onecell_data *clk_data;
44*4882a593Smuzhiyun 	struct device_node *node = pdev->dev.of_node;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
49*4882a593Smuzhiyun 			clk_data);
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun static const struct of_device_id of_match_clk_mt8183_vdec[] = {
55*4882a593Smuzhiyun 	{ .compatible = "mediatek,mt8183-vdecsys", },
56*4882a593Smuzhiyun 	{}
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun static struct platform_driver clk_mt8183_vdec_drv = {
60*4882a593Smuzhiyun 	.probe = clk_mt8183_vdec_probe,
61*4882a593Smuzhiyun 	.driver = {
62*4882a593Smuzhiyun 		.name = "clk-mt8183-vdec",
63*4882a593Smuzhiyun 		.of_match_table = of_match_clk_mt8183_vdec,
64*4882a593Smuzhiyun 	},
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun builtin_platform_driver(clk_mt8183_vdec_drv);
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