1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * R-Car Gen3 Clock Pulse Generator 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015-2018 Glider bvba 6*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Corp. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 11*4882a593Smuzhiyun #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun enum rcar_gen3_clk_types { 14*4882a593Smuzhiyun CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 15*4882a593Smuzhiyun CLK_TYPE_GEN3_PLL0, 16*4882a593Smuzhiyun CLK_TYPE_GEN3_PLL1, 17*4882a593Smuzhiyun CLK_TYPE_GEN3_PLL2, 18*4882a593Smuzhiyun CLK_TYPE_GEN3_PLL3, 19*4882a593Smuzhiyun CLK_TYPE_GEN3_PLL4, 20*4882a593Smuzhiyun CLK_TYPE_GEN3_SD, 21*4882a593Smuzhiyun CLK_TYPE_GEN3_R, 22*4882a593Smuzhiyun CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ 23*4882a593Smuzhiyun CLK_TYPE_GEN3_Z, 24*4882a593Smuzhiyun CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ 25*4882a593Smuzhiyun CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ 26*4882a593Smuzhiyun CLK_TYPE_GEN3_RPCSRC, 27*4882a593Smuzhiyun CLK_TYPE_GEN3_RPC, 28*4882a593Smuzhiyun CLK_TYPE_GEN3_RPCD2, 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* SoC specific definitions start here */ 31*4882a593Smuzhiyun CLK_TYPE_GEN3_SOC_BASE, 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 35*4882a593Smuzhiyun DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 38*4882a593Smuzhiyun DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ 39*4882a593Smuzhiyun (_parent0) << 16 | (_parent1), \ 40*4882a593Smuzhiyun .div = (_div0) << 16 | (_div1), .offset = _md) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 43*4882a593Smuzhiyun _div_clean) \ 44*4882a593Smuzhiyun DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \ 45*4882a593Smuzhiyun _parent_clean, _div_clean) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ 48*4882a593Smuzhiyun DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ 51*4882a593Smuzhiyun DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ 52*4882a593Smuzhiyun (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ 55*4882a593Smuzhiyun DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct rcar_gen3_cpg_pll_config { 58*4882a593Smuzhiyun u8 extal_div; 59*4882a593Smuzhiyun u8 pll1_mult; 60*4882a593Smuzhiyun u8 pll1_div; 61*4882a593Smuzhiyun u8 pll3_mult; 62*4882a593Smuzhiyun u8 pll3_div; 63*4882a593Smuzhiyun u8 osc_prediv; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define CPG_RPCCKCR 0x238 67*4882a593Smuzhiyun #define CPG_RCKCR 0x240 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 70*4882a593Smuzhiyun const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 71*4882a593Smuzhiyun struct clk **clks, void __iomem *base, 72*4882a593Smuzhiyun struct raw_notifier_head *notifiers); 73*4882a593Smuzhiyun int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 74*4882a593Smuzhiyun unsigned int clk_extalr, u32 mode); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif 77