1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Spreadtrum divider clock driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2017 Spreadtrum, Inc.
6*4882a593Smuzhiyun // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _SPRD_DIV_H_
9*4882a593Smuzhiyun #define _SPRD_DIV_H_
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "common.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /**
14*4882a593Smuzhiyun * struct sprd_div_internal - Internal divider description
15*4882a593Smuzhiyun * @shift: Bit offset of the divider in its register
16*4882a593Smuzhiyun * @width: Width of the divider field in its register
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * That structure represents a single divider, and is meant to be
19*4882a593Smuzhiyun * embedded in other structures representing the various clock
20*4882a593Smuzhiyun * classes.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun struct sprd_div_internal {
23*4882a593Smuzhiyun u8 shift;
24*4882a593Smuzhiyun u8 width;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define _SPRD_DIV_CLK(_shift, _width) \
28*4882a593Smuzhiyun { \
29*4882a593Smuzhiyun .shift = _shift, \
30*4882a593Smuzhiyun .width = _width, \
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct sprd_div {
34*4882a593Smuzhiyun struct sprd_div_internal div;
35*4882a593Smuzhiyun struct sprd_clk_common common;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
39*4882a593Smuzhiyun _shift, _width, _flags, _fn) \
40*4882a593Smuzhiyun struct sprd_div _struct = { \
41*4882a593Smuzhiyun .div = _SPRD_DIV_CLK(_shift, _width), \
42*4882a593Smuzhiyun .common = { \
43*4882a593Smuzhiyun .regmap = NULL, \
44*4882a593Smuzhiyun .reg = _reg, \
45*4882a593Smuzhiyun .hw.init = _fn(_name, _parent, \
46*4882a593Smuzhiyun &sprd_div_ops, _flags), \
47*4882a593Smuzhiyun } \
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
51*4882a593Smuzhiyun _shift, _width, _flags) \
52*4882a593Smuzhiyun SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
53*4882a593Smuzhiyun _shift, _width, _flags, CLK_HW_INIT)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \
56*4882a593Smuzhiyun _shift, _width, _flags) \
57*4882a593Smuzhiyun SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
58*4882a593Smuzhiyun _shift, _width, _flags, CLK_HW_INIT_HW)
59*4882a593Smuzhiyun
hw_to_sprd_div(const struct clk_hw * hw)60*4882a593Smuzhiyun static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return container_of(common, struct sprd_div, common);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun long sprd_div_helper_round_rate(struct sprd_clk_common *common,
68*4882a593Smuzhiyun const struct sprd_div_internal *div,
69*4882a593Smuzhiyun unsigned long rate,
70*4882a593Smuzhiyun unsigned long *parent_rate);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
73*4882a593Smuzhiyun const struct sprd_div_internal *div,
74*4882a593Smuzhiyun unsigned long parent_rate);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
77*4882a593Smuzhiyun const struct sprd_div_internal *div,
78*4882a593Smuzhiyun unsigned long rate,
79*4882a593Smuzhiyun unsigned long parent_rate);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun extern const struct clk_ops sprd_div_ops;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #endif /* _SPRD_DIV_H_ */
84