1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef _CCU_NM_H_
7*4882a593Smuzhiyun #define _CCU_NM_H_
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "ccu_common.h"
12*4882a593Smuzhiyun #include "ccu_div.h"
13*4882a593Smuzhiyun #include "ccu_frac.h"
14*4882a593Smuzhiyun #include "ccu_mult.h"
15*4882a593Smuzhiyun #include "ccu_sdm.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * struct ccu_nm - Definition of an N-M clock
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Clocks based on the formula parent * N / M
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun struct ccu_nm {
23*4882a593Smuzhiyun u32 enable;
24*4882a593Smuzhiyun u32 lock;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct ccu_mult_internal n;
27*4882a593Smuzhiyun struct ccu_div_internal m;
28*4882a593Smuzhiyun struct ccu_frac_internal frac;
29*4882a593Smuzhiyun struct ccu_sdm_internal sdm;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun unsigned int fixed_post_div;
32*4882a593Smuzhiyun unsigned int min_rate;
33*4882a593Smuzhiyun unsigned int max_rate;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct ccu_common common;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \
39*4882a593Smuzhiyun _nshift, _nwidth, \
40*4882a593Smuzhiyun _mshift, _mwidth, \
41*4882a593Smuzhiyun _sdm_table, _sdm_en, \
42*4882a593Smuzhiyun _sdm_reg, _sdm_reg_en, \
43*4882a593Smuzhiyun _gate, _lock, _flags) \
44*4882a593Smuzhiyun struct ccu_nm _struct = { \
45*4882a593Smuzhiyun .enable = _gate, \
46*4882a593Smuzhiyun .lock = _lock, \
47*4882a593Smuzhiyun .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
48*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
49*4882a593Smuzhiyun .sdm = _SUNXI_CCU_SDM(_sdm_table, _sdm_en, \
50*4882a593Smuzhiyun _sdm_reg, _sdm_reg_en),\
51*4882a593Smuzhiyun .common = { \
52*4882a593Smuzhiyun .reg = _reg, \
53*4882a593Smuzhiyun .features = CCU_FEATURE_SIGMA_DELTA_MOD, \
54*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
55*4882a593Smuzhiyun _parent, \
56*4882a593Smuzhiyun &ccu_nm_ops, \
57*4882a593Smuzhiyun _flags), \
58*4882a593Smuzhiyun }, \
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \
62*4882a593Smuzhiyun _nshift, _nwidth, \
63*4882a593Smuzhiyun _mshift, _mwidth, \
64*4882a593Smuzhiyun _frac_en, _frac_sel, \
65*4882a593Smuzhiyun _frac_rate_0, _frac_rate_1, \
66*4882a593Smuzhiyun _gate, _lock, _flags) \
67*4882a593Smuzhiyun struct ccu_nm _struct = { \
68*4882a593Smuzhiyun .enable = _gate, \
69*4882a593Smuzhiyun .lock = _lock, \
70*4882a593Smuzhiyun .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
71*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
72*4882a593Smuzhiyun .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
73*4882a593Smuzhiyun _frac_rate_0, \
74*4882a593Smuzhiyun _frac_rate_1), \
75*4882a593Smuzhiyun .common = { \
76*4882a593Smuzhiyun .reg = _reg, \
77*4882a593Smuzhiyun .features = CCU_FEATURE_FRACTIONAL, \
78*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
79*4882a593Smuzhiyun _parent, \
80*4882a593Smuzhiyun &ccu_nm_ops, \
81*4882a593Smuzhiyun _flags), \
82*4882a593Smuzhiyun }, \
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \
86*4882a593Smuzhiyun _reg, _min_rate, \
87*4882a593Smuzhiyun _nshift, _nwidth, \
88*4882a593Smuzhiyun _mshift, _mwidth, \
89*4882a593Smuzhiyun _frac_en, _frac_sel, \
90*4882a593Smuzhiyun _frac_rate_0, _frac_rate_1,\
91*4882a593Smuzhiyun _gate, _lock, _flags) \
92*4882a593Smuzhiyun struct ccu_nm _struct = { \
93*4882a593Smuzhiyun .enable = _gate, \
94*4882a593Smuzhiyun .lock = _lock, \
95*4882a593Smuzhiyun .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
96*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
97*4882a593Smuzhiyun .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
98*4882a593Smuzhiyun _frac_rate_0, \
99*4882a593Smuzhiyun _frac_rate_1), \
100*4882a593Smuzhiyun .min_rate = _min_rate, \
101*4882a593Smuzhiyun .common = { \
102*4882a593Smuzhiyun .reg = _reg, \
103*4882a593Smuzhiyun .features = CCU_FEATURE_FRACTIONAL, \
104*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
105*4882a593Smuzhiyun _parent, \
106*4882a593Smuzhiyun &ccu_nm_ops, \
107*4882a593Smuzhiyun _flags), \
108*4882a593Smuzhiyun }, \
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \
112*4882a593Smuzhiyun _parent, _reg, \
113*4882a593Smuzhiyun _min_rate, _max_rate, \
114*4882a593Smuzhiyun _nshift, _nwidth, \
115*4882a593Smuzhiyun _mshift, _mwidth, \
116*4882a593Smuzhiyun _frac_en, _frac_sel, \
117*4882a593Smuzhiyun _frac_rate_0, \
118*4882a593Smuzhiyun _frac_rate_1, \
119*4882a593Smuzhiyun _gate, _lock, _flags) \
120*4882a593Smuzhiyun struct ccu_nm _struct = { \
121*4882a593Smuzhiyun .enable = _gate, \
122*4882a593Smuzhiyun .lock = _lock, \
123*4882a593Smuzhiyun .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
124*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
125*4882a593Smuzhiyun .frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
126*4882a593Smuzhiyun _frac_rate_0, \
127*4882a593Smuzhiyun _frac_rate_1), \
128*4882a593Smuzhiyun .min_rate = _min_rate, \
129*4882a593Smuzhiyun .max_rate = _max_rate, \
130*4882a593Smuzhiyun .common = { \
131*4882a593Smuzhiyun .reg = _reg, \
132*4882a593Smuzhiyun .features = CCU_FEATURE_FRACTIONAL, \
133*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
134*4882a593Smuzhiyun _parent, \
135*4882a593Smuzhiyun &ccu_nm_ops, \
136*4882a593Smuzhiyun _flags), \
137*4882a593Smuzhiyun }, \
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
141*4882a593Smuzhiyun _nshift, _nwidth, \
142*4882a593Smuzhiyun _mshift, _mwidth, \
143*4882a593Smuzhiyun _gate, _lock, _flags) \
144*4882a593Smuzhiyun struct ccu_nm _struct = { \
145*4882a593Smuzhiyun .enable = _gate, \
146*4882a593Smuzhiyun .lock = _lock, \
147*4882a593Smuzhiyun .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
148*4882a593Smuzhiyun .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
149*4882a593Smuzhiyun .common = { \
150*4882a593Smuzhiyun .reg = _reg, \
151*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
152*4882a593Smuzhiyun _parent, \
153*4882a593Smuzhiyun &ccu_nm_ops, \
154*4882a593Smuzhiyun _flags), \
155*4882a593Smuzhiyun }, \
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
hw_to_ccu_nm(struct clk_hw * hw)158*4882a593Smuzhiyun static inline struct ccu_nm *hw_to_ccu_nm(struct clk_hw *hw)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun struct ccu_common *common = hw_to_ccu_common(hw);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return container_of(common, struct ccu_nm, common);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun extern const struct clk_ops ccu_nm_ops;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun #endif /* _CCU_NM_H_ */
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