1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Spreadtrum pll clock driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2015~2017 Spreadtrum, Inc.
6*4882a593Smuzhiyun // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _SPRD_PLL_H_
9*4882a593Smuzhiyun #define _SPRD_PLL_H_
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "common.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct reg_cfg {
14*4882a593Smuzhiyun u32 val;
15*4882a593Smuzhiyun u32 msk;
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct clk_bit_field {
19*4882a593Smuzhiyun u8 shift;
20*4882a593Smuzhiyun u8 width;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun enum {
24*4882a593Smuzhiyun PLL_LOCK_DONE,
25*4882a593Smuzhiyun PLL_DIV_S,
26*4882a593Smuzhiyun PLL_MOD_EN,
27*4882a593Smuzhiyun PLL_SDM_EN,
28*4882a593Smuzhiyun PLL_REFIN,
29*4882a593Smuzhiyun PLL_IBIAS,
30*4882a593Smuzhiyun PLL_N,
31*4882a593Smuzhiyun PLL_NINT,
32*4882a593Smuzhiyun PLL_KINT,
33*4882a593Smuzhiyun PLL_PREDIV,
34*4882a593Smuzhiyun PLL_POSTDIV,
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun PLL_FACT_MAX
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * struct sprd_pll - definition of adjustable pll clock
41*4882a593Smuzhiyun *
42*4882a593Smuzhiyun * @reg: registers used to set the configuration of pll clock,
43*4882a593Smuzhiyun * reg[0] shows how many registers this pll clock uses.
44*4882a593Smuzhiyun * @itable: pll ibias table, itable[0] means how many items this
45*4882a593Smuzhiyun * table includes
46*4882a593Smuzhiyun * @udelay delay time after setting rate
47*4882a593Smuzhiyun * @factors used to calculate the pll clock rate
48*4882a593Smuzhiyun * @fvco: fvco threshold rate
49*4882a593Smuzhiyun * @fflag: fvco flag
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun struct sprd_pll {
52*4882a593Smuzhiyun u32 regs_num;
53*4882a593Smuzhiyun const u64 *itable;
54*4882a593Smuzhiyun const struct clk_bit_field *factors;
55*4882a593Smuzhiyun u16 udelay;
56*4882a593Smuzhiyun u16 k1;
57*4882a593Smuzhiyun u16 k2;
58*4882a593Smuzhiyun u16 fflag;
59*4882a593Smuzhiyun u64 fvco;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun struct sprd_clk_common common;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \
65*4882a593Smuzhiyun _regs_num, _itable, _factors, \
66*4882a593Smuzhiyun _udelay, _k1, _k2, _fflag, \
67*4882a593Smuzhiyun _fvco, _fn) \
68*4882a593Smuzhiyun struct sprd_pll _struct = { \
69*4882a593Smuzhiyun .regs_num = _regs_num, \
70*4882a593Smuzhiyun .itable = _itable, \
71*4882a593Smuzhiyun .factors = _factors, \
72*4882a593Smuzhiyun .udelay = _udelay, \
73*4882a593Smuzhiyun .k1 = _k1, \
74*4882a593Smuzhiyun .k2 = _k2, \
75*4882a593Smuzhiyun .fflag = _fflag, \
76*4882a593Smuzhiyun .fvco = _fvco, \
77*4882a593Smuzhiyun .common = { \
78*4882a593Smuzhiyun .regmap = NULL, \
79*4882a593Smuzhiyun .reg = _reg, \
80*4882a593Smuzhiyun .hw.init = _fn(_name, _parent, \
81*4882a593Smuzhiyun &sprd_pll_ops, 0),\
82*4882a593Smuzhiyun }, \
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
86*4882a593Smuzhiyun _regs_num, _itable, _factors, \
87*4882a593Smuzhiyun _udelay, _k1, _k2, _fflag, _fvco) \
88*4882a593Smuzhiyun SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
89*4882a593Smuzhiyun _itable, _factors, _udelay, _k1, _k2, \
90*4882a593Smuzhiyun _fflag, _fvco, CLK_HW_INIT)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
93*4882a593Smuzhiyun _regs_num, _itable, _factors, \
94*4882a593Smuzhiyun _udelay, _k1, _k2) \
95*4882a593Smuzhiyun SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
96*4882a593Smuzhiyun _regs_num, _itable, _factors, \
97*4882a593Smuzhiyun _udelay, _k1, _k2, 0, 0)
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \
100*4882a593Smuzhiyun _regs_num, _itable, _factors, _udelay) \
101*4882a593Smuzhiyun SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
102*4882a593Smuzhiyun _regs_num, _itable, _factors, \
103*4882a593Smuzhiyun _udelay, 1000, 1000, 0, 0)
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \
106*4882a593Smuzhiyun _itable, _factors, _udelay, _k1, _k2, \
107*4882a593Smuzhiyun _fflag, _fvco) \
108*4882a593Smuzhiyun SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
109*4882a593Smuzhiyun _itable, _factors, _udelay, _k1, _k2, \
110*4882a593Smuzhiyun _fflag, _fvco, CLK_HW_INIT_FW_NAME)
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun #define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable, \
113*4882a593Smuzhiyun _factors, _udelay, _k1, _k2, _fflag, _fvco) \
114*4882a593Smuzhiyun SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
115*4882a593Smuzhiyun _itable, _factors, _udelay, _k1, _k2, \
116*4882a593Smuzhiyun _fflag, _fvco, CLK_HW_INIT_HW)
117*4882a593Smuzhiyun
hw_to_sprd_pll(struct clk_hw * hw)118*4882a593Smuzhiyun static inline struct sprd_pll *hw_to_sprd_pll(struct clk_hw *hw)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun return container_of(common, struct sprd_pll, common);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun extern const struct clk_ops sprd_pll_ops;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun #endif /* _SPRD_PLL_H_ */
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