1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef _CCU_GATE_H_
7*4882a593Smuzhiyun #define _CCU_GATE_H_
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "ccu_common.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct ccu_gate {
14*4882a593Smuzhiyun u32 enable;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct ccu_common common;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \
20*4882a593Smuzhiyun struct ccu_gate _struct = { \
21*4882a593Smuzhiyun .enable = _gate, \
22*4882a593Smuzhiyun .common = { \
23*4882a593Smuzhiyun .reg = _reg, \
24*4882a593Smuzhiyun .hw.init = CLK_HW_INIT(_name, \
25*4882a593Smuzhiyun _parent, \
26*4882a593Smuzhiyun &ccu_gate_ops, \
27*4882a593Smuzhiyun _flags), \
28*4882a593Smuzhiyun } \
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \
32*4882a593Smuzhiyun struct ccu_gate _struct = { \
33*4882a593Smuzhiyun .enable = _gate, \
34*4882a593Smuzhiyun .common = { \
35*4882a593Smuzhiyun .reg = _reg, \
36*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_HW(_name, \
37*4882a593Smuzhiyun _parent, \
38*4882a593Smuzhiyun &ccu_gate_ops, \
39*4882a593Smuzhiyun _flags), \
40*4882a593Smuzhiyun } \
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \
44*4882a593Smuzhiyun struct ccu_gate _struct = { \
45*4882a593Smuzhiyun .enable = _gate, \
46*4882a593Smuzhiyun .common = { \
47*4882a593Smuzhiyun .reg = _reg, \
48*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_FW_NAME(_name, \
49*4882a593Smuzhiyun _parent, \
50*4882a593Smuzhiyun &ccu_gate_ops, \
51*4882a593Smuzhiyun _flags), \
52*4882a593Smuzhiyun } \
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * The following two macros allow the re-use of the data structure
57*4882a593Smuzhiyun * holding the parent info.
58*4882a593Smuzhiyun */
59*4882a593Smuzhiyun #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \
60*4882a593Smuzhiyun struct ccu_gate _struct = { \
61*4882a593Smuzhiyun .enable = _gate, \
62*4882a593Smuzhiyun .common = { \
63*4882a593Smuzhiyun .reg = _reg, \
64*4882a593Smuzhiyun .hw.init = CLK_HW_INIT_HWS(_name, \
65*4882a593Smuzhiyun _parent, \
66*4882a593Smuzhiyun &ccu_gate_ops, \
67*4882a593Smuzhiyun _flags), \
68*4882a593Smuzhiyun } \
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \
72*4882a593Smuzhiyun struct ccu_gate _struct = { \
73*4882a593Smuzhiyun .enable = _gate, \
74*4882a593Smuzhiyun .common = { \
75*4882a593Smuzhiyun .reg = _reg, \
76*4882a593Smuzhiyun .hw.init = \
77*4882a593Smuzhiyun CLK_HW_INIT_PARENTS_DATA(_name, \
78*4882a593Smuzhiyun _data, \
79*4882a593Smuzhiyun &ccu_gate_ops, \
80*4882a593Smuzhiyun _flags), \
81*4882a593Smuzhiyun } \
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
hw_to_ccu_gate(struct clk_hw * hw)84*4882a593Smuzhiyun static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct ccu_common *common = hw_to_ccu_common(hw);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun return container_of(common, struct ccu_gate, common);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun void ccu_gate_helper_disable(struct ccu_common *common, u32 gate);
92*4882a593Smuzhiyun int ccu_gate_helper_enable(struct ccu_common *common, u32 gate);
93*4882a593Smuzhiyun int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun extern const struct clk_ops ccu_gate_ops;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #endif /* _CCU_GATE_H_ */
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