| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3399-vop-clk-set.dtsi | 17 assigned-clock-parents = <&cru PLL_GPLL>;
23 assigned-clock-parents = <&cru PLL_GPLL>;
28 assigned-clock-parents = <&cru PLL_GPLL>;
33 assigned-clock-parents = <&cru PLL_GPLL>;
38 assigned-clock-parents = <&cru PLL_GPLL>;
48 assigned-clock-parents = <&cru PLL_GPLL>;
53 assigned-clock-parents = <&cru PLL_GPLL>;
58 assigned-clock-parents = <&cru PLL_GPLL>;
63 assigned-clock-parents = <&cru PLL_GPLL>;
78 <&cru PLL_GPLL>, <&cru ACLK_PERIHP>,
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | rv1106-uvc.dtsi | 12 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
46 <&cru PLL_GPLL>, <&cru PLL_GPLL>;
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| H A D | rv1126-evb-uvc.dtsi | 8 <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
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| H A D | rv1103.dtsi | 32 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| H A D | rk3288-evb-rk628-rgb2hdmi-avb.dts | 94 assigned-clock-parents = <&cru PLL_GPLL>;
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| H A D | rk3288-evb-rk628-rgb2lvds-avb.dts | 138 assigned-clock-parents = <&cru PLL_GPLL>;
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| H A D | rk3288-evb-rk628-rgb2lvds-dual-avb.dts | 145 assigned-clock-parents = <&cru PLL_GPLL>;
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| H A D | rk3288-evb-rk628-rgb2dsi-avb.dts | 327 assigned-clock-parents = <&cru PLL_GPLL>;
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| H A D | rk3288-evb-android-rk808-edp-avb.dts | 151 assigned-clock-parents = <&cru PLL_GPLL>;
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 223 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
234 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
794 2, clks[PLL_APLL], clks[PLL_GPLL], in rk3066a_clk_init()
819 2, clks[PLL_APLL], clks[PLL_GPLL], in rk3188a_clk_init()
824 if (clks[ACLK_CPU_PRE] && clks[PLL_GPLL]) { in rk3188a_clk_init()
827 ret = clk_set_parent(clks[ACLK_CPU_PRE], clks[PLL_GPLL]); in rk3188a_clk_init()
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| H A D | clk-rk3036.c | 147 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
486 2, clks[PLL_APLL], clks[PLL_GPLL], in rk3036_clk_init()
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| /OK3568_Linux_fs/u-boot/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 14 #define PLL_GPLL 3 macro
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| H A D | rk3188-cru-common.h | 15 #define PLL_GPLL 4 macro
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| H A D | rk3128-cru.h | 14 #define PLL_GPLL 4 macro
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| H A D | rk3228-cru.h | 14 #define PLL_GPLL 4 macro
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| H A D | rv1108-cru.h | 13 #define PLL_GPLL 2 macro
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| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 13 #define PLL_GPLL 3 macro
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| H A D | rk3188-cru-common.h | 14 #define PLL_GPLL 4 macro
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| H A D | rk3128-cru.h | 14 #define PLL_GPLL 4 macro
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| H A D | rk3228-cru.h | 14 #define PLL_GPLL 4 macro
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3128.c | 69 RK3128_CLK_DUMP(PLL_GPLL, "gpll", true),
87 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK2928_PLL_CON(12),
538 case PLL_GPLL: in rk3128_clk_get_rate()
604 case PLL_GPLL: in rk3128_clk_set_rate()
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| H A D | clk_rk322x.c | 70 RK322x_CLK_DUMP(PLL_GPLL, "gpll", true),
88 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK2928_PLL_CON(9),
585 case PLL_GPLL: in rk322x_clk_get_rate()
653 case PLL_GPLL: in rk322x_clk_set_rate()
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| H A D | clk_rk3328.c | 93 RK3328_CLK_DUMP(PLL_GPLL, "gpll", true),
112 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3328_PLL_CON(24),
803 case PLL_GPLL: in rk3328_clk_get_rate()
884 case PLL_GPLL: in rk3328_clk_set_rate()
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| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | OK3568-C.dts | 110 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL> , <&cru PLL_GPLL>;
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| H A D | .OK3568-C.dtb.pre.tmp | |