1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6&cru { 7 assigned-clocks = 8 <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>, 9 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>, 10 <&cru PLL_HPLL>, <&cru ARMCLK>, 11 <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>, 12 <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>, 13 <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>, 14 <&cru HCLK_PDCORE_NIU>; 15 assigned-clock-rates = 16 <32768>, <1188000000>, 17 <100000000>, <491520000>, 18 <1400000000>, <600000000>, 19 <500000000>, <200000000>, 20 <100000000>, <300000000>, 21 <200000000>, <150000000>, 22 <200000000>; 23}; 24 25&i2s0_8ch { 26 clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>, 27 <&cru MCLK_I2S0_TX_DIV>, <&cru MCLK_I2S0_RX_DIV>, 28 <&cru PLL_CPLL>, <&cru PLL_CPLL>; 29 clock-names = "mclk_tx", "mclk_rx", "hclk", 30 "mclk_tx_src", "mclk_rx_src", 31 "mclk_root0", "mclk_root1"; 32 rockchip,mclk-calibrate; 33}; 34 35