1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun&cru { 7*4882a593Smuzhiyun assigned-clocks = 8*4882a593Smuzhiyun <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>, 9*4882a593Smuzhiyun <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>, 10*4882a593Smuzhiyun <&cru PLL_HPLL>, <&cru ARMCLK>, 11*4882a593Smuzhiyun <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>, 12*4882a593Smuzhiyun <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>, 13*4882a593Smuzhiyun <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>, 14*4882a593Smuzhiyun <&cru HCLK_PDCORE_NIU>; 15*4882a593Smuzhiyun assigned-clock-rates = 16*4882a593Smuzhiyun <32768>, <1188000000>, 17*4882a593Smuzhiyun <100000000>, <491520000>, 18*4882a593Smuzhiyun <1400000000>, <600000000>, 19*4882a593Smuzhiyun <500000000>, <200000000>, 20*4882a593Smuzhiyun <100000000>, <300000000>, 21*4882a593Smuzhiyun <200000000>, <150000000>, 22*4882a593Smuzhiyun <200000000>; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&i2s0_8ch { 26*4882a593Smuzhiyun clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>, 27*4882a593Smuzhiyun <&cru MCLK_I2S0_TX_DIV>, <&cru MCLK_I2S0_RX_DIV>, 28*4882a593Smuzhiyun <&cru PLL_CPLL>, <&cru PLL_CPLL>; 29*4882a593Smuzhiyun clock-names = "mclk_tx", "mclk_rx", "hclk", 30*4882a593Smuzhiyun "mclk_tx_src", "mclk_rx_src", 31*4882a593Smuzhiyun "mclk_root0", "mclk_root1"; 32*4882a593Smuzhiyun rockchip,mclk-calibrate; 33*4882a593Smuzhiyun}; 34*4882a593Smuzhiyun 35